From fa13cd29e261d815d9bd8f9c1d1f8dbaca44f675 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 8 Jul 2021 23:09:49 +0100 Subject: [PATCH] end SVP64 "Vertical First" mode on rollover when end of svstep reached --- src/openpower/decoder/isa/caller.py | 10 ++++++++-- src/openpower/decoder/isa/test_caller_setvl.py | 3 ++- 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py index d8f4d3fc..62bfb6ce 100644 --- a/src/openpower/decoder/isa/caller.py +++ b/src/openpower/decoder/isa/caller.py @@ -1442,11 +1442,14 @@ class ISACaller: yield from self.svstate_pre_inc() pre = yield from self.update_new_svstate_steps() if pre: + # reset at end of loop including exit Vertical Mode log ("SVSTATE_NEXT: end of loop, reset") self.svp64_reset_loop() + self.msr[MSRb.SVF] = 0 self.update_nia() - results = [SelectableInt(0, 64)] - self.handle_comparison(results) # CR0 + if rc_en: + results = [SelectableInt(0, 64)] + self.handle_comparison(results) # CR0 else: log ("SVSTATE_NEXT: post-inc") srcstep, dststep = self.new_srcstep, self.new_dststep @@ -1466,7 +1469,10 @@ class ISACaller: results = [SelectableInt(endtest, 64)] self.handle_comparison(results) # CR0 if end_src or end_dst: + # reset at end of loop including exit Vertical Mode + log ("SVSTATE_NEXT: after increments, reset") self.svp64_reset_loop() + self.msr[MSRb.SVF] = 0 elif self.is_svp64_mode: yield from self.svstate_post_inc() diff --git a/src/openpower/decoder/isa/test_caller_setvl.py b/src/openpower/decoder/isa/test_caller_setvl.py index f4c17058..c6633ee4 100644 --- a/src/openpower/decoder/isa/test_caller_setvl.py +++ b/src/openpower/decoder/isa/test_caller_setvl.py @@ -78,8 +78,9 @@ class DecoderTestCase(FHDLTestCase): self.assertEqual(sim.svstate.dststep.asint(True), 0) print(" gpr1", sim.gpr(0)) self.assertEqual(sim.gpr(0), SelectableInt(0, 64)) + # when end reached, vertical mode is exited print(" msr", bin(sim.msr.value)) - self.assertEqual(sim.msr, SelectableInt(1<<(63-6), 64)) + self.assertEqual(sim.msr, SelectableInt(0<<(63-6), 64)) CR0 = sim.crl[0] print(" CR0", bin(CR0.get_range().value)) self.assertEqual(CR0[CRFields.EQ], 1) -- 2.30.2