From fa1ff71a0f1dd66bd5560fa4cc62e504d5930838 Mon Sep 17 00:00:00 2001 From: Anuj Phogat Date: Mon, 27 Aug 2018 11:23:08 -0700 Subject: [PATCH] i965/icl: Set Enabled Texel Offset Precision Fix bit h/w specification requires this bit to be always set. V2: Fix bit mask (Chris Wilson) Suggested-by: Kenneth Graunke Signed-off-by: Anuj Phogat Reviewed-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/brw_defines.h | 4 ++++ src/mesa/drivers/dri/i965/brw_state_upload.c | 7 +++++++ 2 files changed, 11 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index 433314115b1..97a787a2ab3 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -1673,6 +1673,10 @@ enum brw_pixel_shader_coverage_mask_mode { # define GLK_SCEC_BARRIER_MODE_3D_HULL (1 << 7) # define GLK_SCEC_BARRIER_MODE_MASK REG_MASK(1 << 7) +#define HALF_SLICE_CHICKEN7 0xE194 +# define TEXEL_OFFSET_FIX_ENABLE (1 << 1) +# define TEXEL_OFFSET_FIX_MASK REG_MASK(1 << 1) + #define GEN11_SAMPLER_MODE 0xE18C # define HEADERLESS_MESSAGE_FOR_PREEMPTABLE_CONTEXTS (1 << 5) # define HEADERLESS_MESSAGE_FOR_PREEMPTABLE_CONTEXTS_MASK REG_MASK(1 << 5) diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c index 2af4c45bc44..7f20579fb87 100644 --- a/src/mesa/drivers/dri/i965/brw_state_upload.c +++ b/src/mesa/drivers/dri/i965/brw_state_upload.c @@ -72,6 +72,13 @@ brw_upload_initial_gpu_state(struct brw_context *brw) brw_load_register_imm32(brw, GEN11_SAMPLER_MODE, HEADERLESS_MESSAGE_FOR_PREEMPTABLE_CONTEXTS_MASK | HEADERLESS_MESSAGE_FOR_PREEMPTABLE_CONTEXTS); + + /* Bit 1 "Enabled Texel Offset Precision Fix" must be set in + * HALF_SLICE_CHICKEN7 register. + */ + brw_load_register_imm32(brw, HALF_SLICE_CHICKEN7, + TEXEL_OFFSET_FIX_MASK | + TEXEL_OFFSET_FIX_ENABLE); } if (devinfo->gen == 10 || devinfo->gen == 11) { -- 2.30.2