From fa2331e084ba72708ed4b823fed8571f5a09d9ad Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Thu, 21 Mar 2013 19:02:04 +0100 Subject: [PATCH] dvisampler/clocking: generate pix reset --- milkymist/dvisampler/clocking.py | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/milkymist/dvisampler/clocking.py b/milkymist/dvisampler/clocking.py index b20dfd9b..4d258aa7 100644 --- a/milkymist/dvisampler/clocking.py +++ b/milkymist/dvisampler/clocking.py @@ -66,18 +66,17 @@ class Clocking(Module, AutoReg): self.specials += MultiReg(locked_async, self.locked, "sys") self.comb += self._r_locked.field.w.eq(self.locked) - # sychronize pix5x reset - # this reset is also sampled in the sys clock domain, also guarantee - # a sufficient minimum pulse width. - pix5x_rst_n = 1 - for i in range(5): - new_pix5x_rst_n = Signal() + # sychronize pix+pix5x reset + pix_rst_n = 1 + for i in range(2): + new_pix_rst_n = Signal() self.specials += Instance("FDCE", - Instance.Input("D", pix5x_rst_n), + Instance.Input("D", pix_rst_n), Instance.Input("CE", 1), - Instance.Input("C", ClockSignal("pix5x")), + Instance.Input("C", ClockSignal("pix")), Instance.Input("CLR", ~locked_async), - Instance.Output("Q", new_pix5x_rst_n) + Instance.Output("Q", new_pix_rst_n) ) - pix5x_rst_n = new_pix5x_rst_n - self.comb += self._cd_pix5x.rst.eq(~pix5x_rst_n) + pix_rst_n = new_pix_rst_n + self.comb += self._cd_pix.rst.eq(~pix_rst_n) + self.comb += self._cd_pix5x.rst.eq(~pix_rst_n) -- 2.30.2