From fa4957439907d7053dfa839c43c13e0eae5cef9d Mon Sep 17 00:00:00 2001 From: "Maciej W. Rozycki" Date: Sat, 29 May 2021 03:26:32 +0200 Subject: [PATCH] MIPS/opcodes: Remove DMFC3 and DMTC3 instructions Coprocessor 3 has been removed from the MIPS ISA as from MIPS III[1][2] with the LDC3 and SDC3 instructions having been replaced with LD and SD instructions respectively and therefore the doubleword move instructions from and to that coprocessor have never materialized (for 32-bit ISAs coprocessor 3 has likewise been removed as from MIPS32r2[3]). Remove the DMFC3 and DMTC3 instructions from the opcode table then to avoid confusion. References: [1] Charles Price, "MIPS IV Instruction Set", MIPS Technologies, Inc., Revision 3.2, September, 1995, Section A 8.3.4 "Coprocessor 3 - COP3 and CP3 load/store", p. A-176 [2] same, Table A-39 "CPU Instruction Encoding - MIPS III Architecture", p. A-179 [3] "MIPS32 Architecture For Programmers, Volume II: The MIPS32 Instruction Set", MIPS Technologies, Inc., Document Number: MD00086, Revision 2.00, June 9, 2003, Table A-2 "MIPS32 Encoding of the Opcode Field", p. 317 opcodes/ * mips-opc.c (mips_builtin_opcodes): Remove "dmfc3" and "dmtc3" entries and associated comments. --- opcodes/ChangeLog | 5 +++++ opcodes/mips-opc.c | 4 ---- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 2e93d56aa0c..955c4b3b531 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,8 @@ +2021-05-29 Maciej W. Rozycki + + * mips-opc.c (mips_builtin_opcodes): Remove "dmfc3" and "dmtc3" + entries and associated comments. + 2021-05-29 Maciej W. Rozycki * mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c index 210d0149920..a80e98164bf 100644 --- a/opcodes/mips-opc.c +++ b/opcodes/mips-opc.c @@ -1112,8 +1112,6 @@ const struct mips_opcode mips_builtin_opcodes[] = {"dmtc1", "t,G", 0x44a00000, 0xffe007ff, RD_1|WR_2|CM|FP_D, 0, I3, 0, SF }, /* dmfc2 is at the bottom of the table. */ /* dmtc2 is at the bottom of the table. */ -/* dmfc3 is at the bottom of the table. */ -/* dmtc3 is at the bottom of the table. */ {"dmuh", "d,s,t", 0x000000dc, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I69, 0, 0 }, {"dmul", "d,s,t", 0x0000009c, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I69, 0, 0 }, {"dmul", "d,v,t", 0x70000003, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, IOCT, 0, 0 }, @@ -2161,8 +2159,6 @@ const struct mips_opcode mips_builtin_opcodes[] = {"bc3tl", "p", 0x4d030000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, IOCT|IOCTP|IOCT2|EE|I37 }, {"cfc3", "t,g", 0x4c400000, 0xffe007ff, WR_1|RD_C3|LC, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 }, {"ctc3", "t,g", 0x4cc00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 }, -{"dmfc3", "t,G", 0x4c200000, 0xffe007ff, WR_1|RD_C3|LC, 0, I3, 0, IOCT|IOCTP|IOCT2|EE|I37 }, -{"dmtc3", "t,G", 0x4ca00000, 0xffe007ff, RD_1|WR_C3|WR_CC|CM, 0, I3, 0, IOCT|IOCTP|IOCT2|EE|I37 }, {"mfc3", "t,G", 0x4c000000, 0xffe007ff, WR_1|RD_C3|LC, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 }, {"mfc3", "t,G,H", 0x4c000000, 0xffe007f8, WR_1|RD_C3|LC, 0, I32, 0, IOCT|IOCTP|IOCT2|EE|I37 }, {"mtc3", "t,G", 0x4c800000, 0xffe007ff, RD_1|WR_C3|WR_CC|CM, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 }, -- 2.30.2