From fa59bcdca8b077ee93b00b39b01f45ac2cc09ea6 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sat, 23 Oct 2021 18:53:40 +0100 Subject: [PATCH] --- 3d_gpu/architecture/dynamic_simd/slice.mdwn | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/3d_gpu/architecture/dynamic_simd/slice.mdwn b/3d_gpu/architecture/dynamic_simd/slice.mdwn index f17648ca0..59f44212f 100644 --- a/3d_gpu/architecture/dynamic_simd/slice.mdwn +++ b/3d_gpu/architecture/dynamic_simd/slice.mdwn @@ -175,11 +175,13 @@ take signal a, of 16 bits, each bit being numbered in hexadecimal: | | | AfAeAdAc AbAaA9A8 A7A6A5A4 A3A2A1A0 -and take a slice a[0:2] to create 3-bit values, where padding is +and take a slice a[0:1] to create 3-bit values, where padding is specified by "x", at each elwid: elwid | | | - 0b00 AfAeAdAc AbAaA9A8 A7A6A5A4 A3A2A1A0 + 0b00 x x x x x x x x x x x x x A2A1A0 + 0b01 x x x x x AaA9A8 x x x x x A2A1A0 + 0b10 x AeAdAc x AaA9A8 x A6A5A4 x A2A1A0 Illustrating the case where a Sliced (fixed element width) SimdSignal is added to one which has variable-length elements that take up the -- 2.30.2