From fa617be7012eda159a65cb78ae1a7e2ccbf8ab8f Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Sat, 23 May 2020 19:06:44 +0100
Subject: [PATCH]

---
 3d_gpu/architecture/regfile.mdwn | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/3d_gpu/architecture/regfile.mdwn b/3d_gpu/architecture/regfile.mdwn
index 8f5f04d69..86e69944b 100644
--- a/3d_gpu/architecture/regfile.mdwn
+++ b/3d_gpu/architecture/regfile.mdwn
@@ -83,6 +83,8 @@ Regspecs are defined, in python, as follows:
 | ----         | ----------           | ------------               |
 | INT          | ra                   | 0:3,5                      |
 
+Description of each heading:
+
 * Regfile name: INT corresponds to the INTEGER file, CR to Condition Register etc.
 * CompUnit Record name: in the Input or Output Record there will be a signal by
   name.  This field refers to that record signal, thus providing a sequential
-- 
2.30.2