From fa68cc4e58ac1bcdf81a6c7d8da51f61b210b9bb Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 22 Mar 2018 11:27:49 +0000 Subject: [PATCH] attempt to add io_interface to iface automatically --- src/interface_decl.py | 4 ++-- src/pinmux_generator.py | 7 +++++-- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/src/interface_decl.py b/src/interface_decl.py index cae4e37..c6da931 100644 --- a/src/interface_decl.py +++ b/src/interface_decl.py @@ -253,8 +253,6 @@ io_interface = IOInterface('io', # Outputs from the peripherals will be inputs to the pinmux # module. Hence the change in direction for most pins -ifaces = Interfaces() - # ======================================= # # basic test @@ -302,6 +300,8 @@ if __name__ == '__main__': print assert p1 == p2 + ifaces = Interfaces() + ifaceuart = ifaces['uart'] print ifaceuart.ifacedef(0) print uartinterface_decl.ifacedef(0) diff --git a/src/pinmux_generator.py b/src/pinmux_generator.py index f3e00cd..fa7e3a7 100644 --- a/src/pinmux_generator.py +++ b/src/pinmux_generator.py @@ -22,7 +22,7 @@ import time import math # project module imports -from interface_decl import ifaces, mux_interface, io_interface +from interface_decl import Interfaces, mux_interface, io_interface from wire_def import muxwire, generic_io from parse import Parse from actual_pinmux import init @@ -30,6 +30,8 @@ from bus_transactors import axi4_lite p = Parse() init(p) +ifaces = Interfaces() +#ifaces.ifaceadd('io', p.N_IO, io_interface) if not os.path.exists("bsv_src"): os.makedirs("bsv_src") @@ -91,7 +93,8 @@ with open("./bsv_src/pinmux.bsv", "w") as bsv_file: // Each IO cell will have 8 input field (output from pin mux // and on output field (input to pinmux)''') for i in range(0, p.N_IO): - bsv_file.write('''\n // interface for IO CEll-{0}''') + bsv_file.write('''\n // interface declaration between IO-{0} and pinmux'''.format(i)) + bsv_file.write(io_interface.ifacefmt(i)) # ============================================================== -- 2.30.2