From fa758a70467c37cfe7b261e1dc20d431be3db62e Mon Sep 17 00:00:00 2001 From: Alex Chadwick Date: Tue, 24 Jul 2018 09:21:44 +0930 Subject: [PATCH] PowerPC Improve support for Gekko & Broadway This is a relatively straightforward patch to improve support for the IBM Gekko and IBM Broadway processors. Broadway is functionally equivalent to the IBM 750CL, while Gekko's functionality is a subset of theirs. The patch simplifies this reality and adds -mgekko and -mbroadway as aliases for -m750cl. I didn't feel it was worth wasting a PPC_OPCODE_* bit to differentiate Gekko. The patch adds a number of simplified mnemonics for special purpose register access. Notably, Broadway adds 4 additional IBAT and DBAT registers but these are not assigned sequential SPR numbers. gas/ * config/tc-ppc.c (md_show_usage): Add -mgekko and -mbroadway. * doc/as.texi (Target PowerPC options): Add -mgekko and -mbroadway. * doc/c-ppc.texi (PowerPC-Opts): Likewise. * testsuite/gas/ppc/broadway.d, * testsuite/gas/ppc/broadway.s: New test for broadway. * testsuite/gas/ppc/ppc.exp: Run new test. include/ * opcode/ppc.h (PPC_OPCODE_750): Adjust comment. opcodes/ * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway. (powerpc_init_dialect): Handle bfd_mach_ppc_750. * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to support disjointed BAT. (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR. (XSPRGQR_MASK, GEKKO, BROADWAY): Define. (powerpc_opcodes): Add 750cl extended mnemonics for spr access. --- gas/ChangeLog | 9 +++ gas/config/tc-ppc.c | 3 +- gas/doc/as.texi | 8 +-- gas/doc/c-ppc.texi | 4 +- gas/testsuite/gas/ppc/broadway.d | 108 +++++++++++++++++++++++++++++++ gas/testsuite/gas/ppc/broadway.s | 103 +++++++++++++++++++++++++++++ gas/testsuite/gas/ppc/ppc.exp | 1 + include/ChangeLog | 4 ++ include/opcode/ppc.h | 2 +- opcodes/ChangeLog | 11 ++++ opcodes/ppc-dis.c | 7 ++ opcodes/ppc-opc.c | 76 ++++++++++++++++++++-- 12 files changed, 323 insertions(+), 13 deletions(-) create mode 100644 gas/testsuite/gas/ppc/broadway.d create mode 100644 gas/testsuite/gas/ppc/broadway.s diff --git a/gas/ChangeLog b/gas/ChangeLog index fa8a7c5496f..582a12d0ee3 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,12 @@ +2018-07-26 Alex Chadwick + + * config/tc-ppc.c (md_show_usage): Add -mgekko and -mbroadway. + * doc/as.texi (Target PowerPC options): Add -mgekko and -mbroadway. + * doc/c-ppc.texi (PowerPC-Opts): Likewise. + * testsuite/gas/ppc/broadway.d, + * testsuite/gas/ppc/broadway.s: New test for broadway. + * testsuite/gas/ppc/ppc.exp: Run new test. + 2018-07-26 Alan Modra * config/tc-ppc.c (ppc_elf_localentry): Allow .localentry values diff --git a/gas/config/tc-ppc.c b/gas/config/tc-ppc.c index 4388b2570b9..eaa866dbd29 100644 --- a/gas/config/tc-ppc.c +++ b/gas/config/tc-ppc.c @@ -1340,7 +1340,8 @@ PowerPC options:\n\ -m476 generate code for PowerPC 476\n\ -m7400, -m7410, -m7450, -m7455\n\ generate code for PowerPC 7400/7410/7450/7455\n\ --m750cl generate code for PowerPC 750cl\n\ +-m750cl, -mgekko, -mbroadway\n\ + generate code for PowerPC 750cl/Gekko/Broadway\n\ -m821, -m850, -m860 generate code for PowerPC 821/850/860\n")); fprintf (stream, _("\ -mppc64, -m620 generate code for PowerPC 620/625/630\n\ diff --git a/gas/doc/as.texi b/gas/doc/as.texi index e9b6016aaa4..aea5e711054 100644 --- a/gas/doc/as.texi +++ b/gas/doc/as.texi @@ -476,10 +476,10 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}. @emph{Target PowerPC options:} [@b{-a32}|@b{-a64}] [@b{-mpwrx}|@b{-mpwr2}|@b{-mpwr}|@b{-m601}|@b{-mppc}|@b{-mppc32}|@b{-m603}|@b{-m604}|@b{-m403}|@b{-m405}| - @b{-m440}|@b{-m464}|@b{-m476}|@b{-m7400}|@b{-m7410}|@b{-m7450}|@b{-m7455}|@b{-m750cl}|@b{-mppc64}| - @b{-m620}|@b{-me500}|@b{-e500x2}|@b{-me500mc}|@b{-me500mc64}|@b{-me5500}|@b{-me6500}|@b{-mppc64bridge}| - @b{-mbooke}|@b{-mpower4}|@b{-mpwr4}|@b{-mpower5}|@b{-mpwr5}|@b{-mpwr5x}|@b{-mpower6}|@b{-mpwr6}| - @b{-mpower7}|@b{-mpwr7}|@b{-mpower8}|@b{-mpwr8}|@b{-mpower9}|@b{-mpwr9}@b{-ma2}| + @b{-m440}|@b{-m464}|@b{-m476}|@b{-m7400}|@b{-m7410}|@b{-m7450}|@b{-m7455}|@b{-m750cl}|@b{-mgekko}| + @b{-mbroadway}|@b{-mppc64}|@b{-m620}|@b{-me500}|@b{-e500x2}|@b{-me500mc}|@b{-me500mc64}|@b{-me5500}| + @b{-me6500}|@b{-mppc64bridge}|@b{-mbooke}|@b{-mpower4}|@b{-mpwr4}|@b{-mpower5}|@b{-mpwr5}|@b{-mpwr5x}| + @b{-mpower6}|@b{-mpwr6}|@b{-mpower7}|@b{-mpwr7}|@b{-mpower8}|@b{-mpwr8}|@b{-mpower9}|@b{-mpwr9}@b{-ma2}| @b{-mcell}|@b{-mspe}|@b{-mspe2}|@b{-mtitan}|@b{-me300}|@b{-mcom}] [@b{-many}] [@b{-maltivec}|@b{-mvsx}|@b{-mhtm}|@b{-mvle}] [@b{-mregnames}|@b{-mno-regnames}] diff --git a/gas/doc/c-ppc.texi b/gas/doc/c-ppc.texi index 6f7b0f9a91e..dfab8a6c806 100644 --- a/gas/doc/c-ppc.texi +++ b/gas/doc/c-ppc.texi @@ -72,8 +72,8 @@ Generate code for PowerPC 476. @item -m7400, -m7410, -m7450, -m7455 Generate code for PowerPC 7400/7410/7450/7455. -@item -m750cl -Generate code for PowerPC 750CL. +@item -m750cl, -mgekko, -mbroadway +Generate code for PowerPC 750CL/Gekko/Broadway. @item -m821, -m850, -m860 Generate code for PowerPC 821/850/860. diff --git a/gas/testsuite/gas/ppc/broadway.d b/gas/testsuite/gas/ppc/broadway.d new file mode 100644 index 00000000000..136e2ef8412 --- /dev/null +++ b/gas/testsuite/gas/ppc/broadway.d @@ -0,0 +1,108 @@ +#as: -mbroadway +#objdump: -dr -Mbroadway +#name: PPC Broadway instructions + +.* + +Disassembly of section \.text: + +0+0000000 : + 0: (7c 12 fa a6|a6 fa 12 7c) mfiabr r0 + 4: (7c 32 fb a6|a6 fb 32 7c) mtiabr r1 + 8: (7c 55 fa a6|a6 fa 55 7c) mfdabr r2 + c: (7c 75 fb a6|a6 fb 75 7c) mtdabr r3 + 10: (7c 90 e2 a6|a6 e2 90 7c) mfgqr r4,0 + 14: (7c b1 e2 a6|a6 e2 b1 7c) mfgqr r5,1 + 18: (7c d2 e2 a6|a6 e2 d2 7c) mfgqr r6,2 + 1c: (7c f3 e2 a6|a6 e2 f3 7c) mfgqr r7,3 + 20: (7d 14 e2 a6|a6 e2 14 7d) mfgqr r8,4 + 24: (7d 35 e2 a6|a6 e2 35 7d) mfgqr r9,5 + 28: (7d 56 e2 a6|a6 e2 56 7d) mfgqr r10,6 + 2c: (7d 77 e2 a6|a6 e2 77 7d) mfgqr r11,7 + 30: (7c 90 e3 a6|a6 e3 90 7c) mtgqr 0,r4 + 34: (7c b1 e3 a6|a6 e3 b1 7c) mtgqr 1,r5 + 38: (7c d2 e3 a6|a6 e3 d2 7c) mtgqr 2,r6 + 3c: (7c f3 e3 a6|a6 e3 f3 7c) mtgqr 3,r7 + 40: (7d 14 e3 a6|a6 e3 14 7d) mtgqr 4,r8 + 44: (7d 35 e3 a6|a6 e3 35 7d) mtgqr 5,r9 + 48: (7d 56 e3 a6|a6 e3 56 7d) mtgqr 6,r10 + 4c: (7d 77 e3 a6|a6 e3 77 7d) mtgqr 7,r11 + 50: (7d 99 e2 a6|a6 e2 99 7d) mfwpar r12 + 54: (7d b9 e3 a6|a6 e3 b9 7d) mtwpar r13 + 58: (7d db e2 a6|a6 e2 db 7d) mfdmal r14 + 5c: (7d fb e3 a6|a6 e3 fb 7d) mtdmal r15 + 60: (7e 1a e2 a6|a6 e2 1a 7e) mfdmau r16 + 64: (7e 3a e3 a6|a6 e3 3a 7e) mtdmau r17 + 68: (7e 50 fa a6|a6 fa 50 7e) mfhid0 r18 + 6c: (7e 70 fb a6|a6 fb 70 7e) mthid0 r19 + 70: (7e 91 fa a6|a6 fa 91 7e) mfhid1 r20 + 74: (7e b1 fb a6|a6 fb b1 7e) mthid1 r21 + 78: (7e d8 e2 a6|a6 e2 d8 7e) mfhid2 r22 + 7c: (7e f8 e3 a6|a6 e3 f8 7e) mthid2 r23 + 80: (7f 13 fa a6|a6 fa 13 7f) mfhid4 r24 + 84: (7f 33 fb a6|a6 fb 33 7f) mthid4 r25 + 88: (7c 10 82 a6|a6 82 10 7c) mfibatu r0,0 + 8c: (7c 30 83 a6|a6 83 30 7c) mtibatu 0,r1 + 90: (7c 52 82 a6|a6 82 52 7c) mfibatu r2,1 + 94: (7c 72 83 a6|a6 83 72 7c) mtibatu 1,r3 + 98: (7c 94 82 a6|a6 82 94 7c) mfibatu r4,2 + 9c: (7c b4 83 a6|a6 83 b4 7c) mtibatu 2,r5 + a0: (7c d6 82 a6|a6 82 d6 7c) mfibatu r6,3 + a4: (7c f6 83 a6|a6 83 f6 7c) mtibatu 3,r7 + a8: (7d 10 8a a6|a6 8a 10 7d) mfibatu r8,4 + ac: (7d 30 8b a6|a6 8b 30 7d) mtibatu 4,r9 + b0: (7d 52 8a a6|a6 8a 52 7d) mfibatu r10,5 + b4: (7d 72 8b a6|a6 8b 72 7d) mtibatu 5,r11 + b8: (7d 94 8a a6|a6 8a 94 7d) mfibatu r12,6 + bc: (7d b4 8b a6|a6 8b b4 7d) mtibatu 6,r13 + c0: (7d d6 8a a6|a6 8a d6 7d) mfibatu r14,7 + c4: (7d f6 8b a6|a6 8b f6 7d) mtibatu 7,r15 + c8: (7e 11 82 a6|a6 82 11 7e) mfibatl r16,0 + cc: (7e 31 83 a6|a6 83 31 7e) mtibatl 0,r17 + d0: (7e 53 82 a6|a6 82 53 7e) mfibatl r18,1 + d4: (7e 73 83 a6|a6 83 73 7e) mtibatl 1,r19 + d8: (7e 95 82 a6|a6 82 95 7e) mfibatl r20,2 + dc: (7e b5 83 a6|a6 83 b5 7e) mtibatl 2,r21 + e0: (7e d7 82 a6|a6 82 d7 7e) mfibatl r22,3 + e4: (7e f7 83 a6|a6 83 f7 7e) mtibatl 3,r23 + e8: (7f 11 8a a6|a6 8a 11 7f) mfibatl r24,4 + ec: (7f 31 8b a6|a6 8b 31 7f) mtibatl 4,r25 + f0: (7f 53 8a a6|a6 8a 53 7f) mfibatl r26,5 + f4: (7f 73 8b a6|a6 8b 73 7f) mtibatl 5,r27 + f8: (7f 95 8a a6|a6 8a 95 7f) mfibatl r28,6 + fc: (7f b5 8b a6|a6 8b b5 7f) mtibatl 6,r29 + 100: (7f d7 8a a6|a6 8a d7 7f) mfibatl r30,7 + 104: (7f f7 8b a6|a6 8b f7 7f) mtibatl 7,r31 + 108: (7c 18 82 a6|a6 82 18 7c) mfdbatu r0,0 + 10c: (7c 38 83 a6|a6 83 38 7c) mtdbatu 0,r1 + 110: (7c 5a 82 a6|a6 82 5a 7c) mfdbatu r2,1 + 114: (7c 7a 83 a6|a6 83 7a 7c) mtdbatu 1,r3 + 118: (7c 9c 82 a6|a6 82 9c 7c) mfdbatu r4,2 + 11c: (7c bc 83 a6|a6 83 bc 7c) mtdbatu 2,r5 + 120: (7c de 82 a6|a6 82 de 7c) mfdbatu r6,3 + 124: (7c fe 83 a6|a6 83 fe 7c) mtdbatu 3,r7 + 128: (7d 18 8a a6|a6 8a 18 7d) mfdbatu r8,4 + 12c: (7d 38 8b a6|a6 8b 38 7d) mtdbatu 4,r9 + 130: (7d 5a 8a a6|a6 8a 5a 7d) mfdbatu r10,5 + 134: (7d 7a 8b a6|a6 8b 7a 7d) mtdbatu 5,r11 + 138: (7d 9c 8a a6|a6 8a 9c 7d) mfdbatu r12,6 + 13c: (7d bc 8b a6|a6 8b bc 7d) mtdbatu 6,r13 + 140: (7d de 8a a6|a6 8a de 7d) mfdbatu r14,7 + 144: (7d fe 8b a6|a6 8b fe 7d) mtdbatu 7,r15 + 148: (7e 19 82 a6|a6 82 19 7e) mfdbatl r16,0 + 14c: (7e 39 83 a6|a6 83 39 7e) mtdbatl 0,r17 + 150: (7e 5b 82 a6|a6 82 5b 7e) mfdbatl r18,1 + 154: (7e 7b 83 a6|a6 83 7b 7e) mtdbatl 1,r19 + 158: (7e 9d 82 a6|a6 82 9d 7e) mfdbatl r20,2 + 15c: (7e bd 83 a6|a6 83 bd 7e) mtdbatl 2,r21 + 160: (7e df 82 a6|a6 82 df 7e) mfdbatl r22,3 + 164: (7e ff 83 a6|a6 83 ff 7e) mtdbatl 3,r23 + 168: (7f 19 8a a6|a6 8a 19 7f) mfdbatl r24,4 + 16c: (7f 39 8b a6|a6 8b 39 7f) mtdbatl 4,r25 + 170: (7f 5b 8a a6|a6 8a 5b 7f) mfdbatl r26,5 + 174: (7f 7b 8b a6|a6 8b 7b 7f) mtdbatl 5,r27 + 178: (7f 9d 8a a6|a6 8a 9d 7f) mfdbatl r28,6 + 17c: (7f bd 8b a6|a6 8b bd 7f) mtdbatl 6,r29 + 180: (7f df 8a a6|a6 8a df 7f) mfdbatl r30,7 + 184: (7f ff 8b a6|a6 8b ff 7f) mtdbatl 7,r31 +#pass diff --git a/gas/testsuite/gas/ppc/broadway.s b/gas/testsuite/gas/ppc/broadway.s new file mode 100644 index 00000000000..b8c4b7bbee7 --- /dev/null +++ b/gas/testsuite/gas/ppc/broadway.s @@ -0,0 +1,103 @@ +# PowerPC Broadway instruction tests + .text +start: + mfiabr 0 + mtiabr 1 + mfdabr 2 + mtdabr 3 + mfgqr 4, 0 + mfgqr 5, 1 + mfgqr 6, 2 + mfgqr 7, 3 + mfgqr 8, 4 + mfgqr 9, 5 + mfgqr 10, 6 + mfgqr 11, 7 + mtgqr 0, 4 + mtgqr 1, 5 + mtgqr 2, 6 + mtgqr 3, 7 + mtgqr 4, 8 + mtgqr 5, 9 + mtgqr 6, 10 + mtgqr 7, 11 + mfwpar 12 + mtwpar 13 + mfdmal 14 + mtdmal 15 + mfdmau 16 + mtdmau 17 + mfhid0 18 + mthid0 19 + mfhid1 20 + mthid1 21 + mfhid2 22 + mthid2 23 + mfhid4 24 + mthid4 25 + + mfibatu 0, 0 + mtibatu 0, 1 + mfibatu 2, 1 + mtibatu 1, 3 + mfibatu 4, 2 + mtibatu 2, 5 + mfibatu 6, 3 + mtibatu 3, 7 + mfibatu 8, 4 + mtibatu 4, 9 + mfibatu 10, 5 + mtibatu 5, 11 + mfibatu 12, 6 + mtibatu 6, 13 + mfibatu 14, 7 + mtibatu 7, 15 + mfibatl 16, 0 + mtibatl 0, 17 + mfibatl 18, 1 + mtibatl 1, 19 + mfibatl 20, 2 + mtibatl 2, 21 + mfibatl 22, 3 + mtibatl 3, 23 + mfibatl 24, 4 + mtibatl 4, 25 + mfibatl 26, 5 + mtibatl 5, 27 + mfibatl 28, 6 + mtibatl 6, 29 + mfibatl 30, 7 + mtibatl 7, 31 + + mfdbatu 0, 0 + mtdbatu 0, 1 + mfdbatu 2, 1 + mtdbatu 1, 3 + mfdbatu 4, 2 + mtdbatu 2, 5 + mfdbatu 6, 3 + mtdbatu 3, 7 + mfdbatu 8, 4 + mtdbatu 4, 9 + mfdbatu 10, 5 + mtdbatu 5, 11 + mfdbatu 12, 6 + mtdbatu 6, 13 + mfdbatu 14, 7 + mtdbatu 7, 15 + mfdbatl 16, 0 + mtdbatl 0, 17 + mfdbatl 18, 1 + mtdbatl 1, 19 + mfdbatl 20, 2 + mtdbatl 2, 21 + mfdbatl 22, 3 + mtdbatl 3, 23 + mfdbatl 24, 4 + mtdbatl 4, 25 + mfdbatl 26, 5 + mtdbatl 5, 27 + mfdbatl 28, 6 + mtdbatl 6, 29 + mfdbatl 30, 7 + mtdbatl 7, 31 diff --git a/gas/testsuite/gas/ppc/ppc.exp b/gas/testsuite/gas/ppc/ppc.exp index f3b37de1bf5..f36d0157775 100644 --- a/gas/testsuite/gas/ppc/ppc.exp +++ b/gas/testsuite/gas/ppc/ppc.exp @@ -90,6 +90,7 @@ run_dump_test "spe_ambiguous" run_dump_test "altivec" run_dump_test "altivec2" run_dump_test "altivec3" +run_dump_test "broadway" run_dump_test "booke" run_dump_test "e500" run_list_test "e500-ill" "-me500" diff --git a/include/ChangeLog b/include/ChangeLog index 8558368463a..d39f52e6e95 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,7 @@ +2018-07-26 Alex Chadwick + + * opcode/ppc.h (PPC_OPCODE_750): Adjust comment. + 2018-07-26 Alan Modra * elf/ppc64.h: Specify byte offset to local entry for values diff --git a/include/opcode/ppc.h b/include/opcode/ppc.h index 44445bcad22..cfabcbd097e 100644 --- a/include/opcode/ppc.h +++ b/include/opcode/ppc.h @@ -204,7 +204,7 @@ extern const unsigned int spe2_num_opcodes; /* Opcode is only supported by Power8 architecture. */ #define PPC_OPCODE_POWER8 0x1000000000ull -/* Opcode is supported by ppc750cl. */ +/* Opcode is supported by ppc750cl/Gekko/Broadway. */ #define PPC_OPCODE_750 0x2000000000ull /* Opcode is supported by ppc7450. */ diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 6452989160a..88286afb4d2 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,14 @@ +2018-07-26 Alex Chadwick + Alan Modra + + * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway. + (powerpc_init_dialect): Handle bfd_mach_ppc_750. + * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to + support disjointed BAT. + (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR. + (XSPRGQR_MASK, GEKKO, BROADWAY): Define. + (powerpc_opcodes): Add 750cl extended mnemonics for spr access. + 2018-07-25 H.J. Lu Igor Tsimbalist diff --git a/opcodes/ppc-dis.c b/opcodes/ppc-dis.c index bd6072ef0c1..035767c9036 100644 --- a/opcodes/ppc-dis.c +++ b/opcodes/ppc-dis.c @@ -94,6 +94,10 @@ struct ppc_mopt ppc_opts[] = { 0 }, { "750cl", PPC_OPCODE_PPC | PPC_OPCODE_750 | PPC_OPCODE_PPCPS , 0 }, + { "gekko", PPC_OPCODE_PPC | PPC_OPCODE_750 | PPC_OPCODE_PPCPS + , 0 }, + { "broadway", PPC_OPCODE_PPC | PPC_OPCODE_750 | PPC_OPCODE_PPCPS + , 0 }, { "821", PPC_OPCODE_PPC | PPC_OPCODE_860, 0 }, { "850", PPC_OPCODE_PPC | PPC_OPCODE_860, @@ -313,6 +317,9 @@ powerpc_init_dialect (struct disassemble_info *info) case bfd_mach_ppc_601: dialect = ppc_parse_cpu (dialect, &sticky, "601"); break; + case bfd_mach_ppc_750: + dialect = ppc_parse_cpu (dialect, &sticky, "750cl"); + break; case bfd_mach_ppc_a35: case bfd_mach_ppc_rs64ii: case bfd_mach_ppc_rs64iii: diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c index ba1bd3bb690..03891a47181 100644 --- a/opcodes/ppc-opc.c +++ b/opcodes/ppc-opc.c @@ -1187,6 +1187,41 @@ extract_spr (uint64_t insn, return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0); } +/* Some dialects have 8 [DI]BAT registers instead of the standard 4. */ +#define ALLOW8_BAT (PPC_OPCODE_750) + +static unsigned long +insert_sprbat (unsigned long insn, + long value, + ppc_cpu_t dialect, + const char **errmsg) +{ + if (value > 7 + || (value > 3 && (dialect & ALLOW8_BAT) == 0)) + *errmsg = _("invalid bat number"); + + /* If this is [di]bat4..7 then use spr 560..575, otherwise 528..543. */ + if (value > 3) + value = ((value & 3) << 6) | 1; + else + value = value << 6; + + return insn | (value << 11); +} + +static long +extract_sprbat (unsigned long insn, + ppc_cpu_t dialect, + int *invalid) +{ + unsigned long val = (insn >> 17) & 0x3; + + val = val + ((insn >> 9) & 0x4); + if (val > 3 && (dialect & ALLOW8_BAT) == 0) + *invalid = 1; + return val; +} + /* Some dialects have 8 SPRG registers instead of the standard 4. */ #define ALLOW8_SPRG (PPC_OPCODE_BOOKE | PPC_OPCODE_405) @@ -2305,11 +2340,16 @@ const struct powerpc_operand powerpc_operands[] = /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */ #define SPRBAT SPR + 1 -#define SPRBAT_MASK (0x3 << 17) - { 0x3, 17, NULL, NULL, 0 }, +#define SPRBAT_MASK (0xc1 << 11) + { 0x7, PPC_OPSHIFT_INV, insert_sprbat, extract_sprbat, PPC_OPERAND_SPR }, + + /* The GQR index number in an XFX form m[ft]gqr instruction. */ +#define SPRGQR SPRBAT + 1 +#define SPRGQR_MASK (0x7 << 16) + { 0x7, 16, NULL, NULL, PPC_OPERAND_GQR }, /* The SPRG register number in an XFX form m[ft]sprg instruction. */ -#define SPRG SPRBAT + 1 +#define SPRG SPRGQR + 1 { 0x1f, 16, insert_sprg, extract_sprg, PPC_OPERAND_SPR }, /* The SR field in an X form instruction. */ @@ -3365,6 +3405,10 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands) SPRBAT field. */ #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK) +/* An XFX form instruction with the SPR field filled in except for the + SPRGQR field. */ +#define XSPRGQR_MASK (XSPR_MASK &~ SPRGQR_MASK) + /* An XFX form instruction with the SPR field filled in except for the SPRG field. */ #define XSPRG_MASK (XSPR_MASK & ~(0x1f << 16)) @@ -3480,6 +3524,8 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands) #define PPC464 PPC440 #define PPC476 PPC_OPCODE_476 #define PPC750 PPC_OPCODE_750 +#define GEKKO PPC_OPCODE_750 +#define BROADWAY PPC_OPCODE_750 #define PPC7450 PPC_OPCODE_7450 #define PPC860 PPC_OPCODE_860 #define PPCPS PPC_OPCODE_PPCPS @@ -3512,7 +3558,7 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands) #define PPCPMR PPC_OPCODE_PMR #define PPCTMR PPC_OPCODE_TMR #define PPCCHLK PPC_OPCODE_CACHELCK -#define PPCRFMCI PPC_OPCODE_RFMCI +#define PPCRFMCI PPC_OPCODE_RFMCI #define E500MC PPC_OPCODE_E500MC #define PPCA2 PPC_OPCODE_A2 #define TITAN PPC_OPCODE_TITAN @@ -5939,6 +5985,11 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"mfccr1", XSPR(31,339,888), XSPR_MASK, TITAN, 0, {RT}}, {"mfppr", XSPR(31,339,896), XSPR_MASK, POWER7, 0, {RT}}, {"mfppr32", XSPR(31,339,898), XSPR_MASK, POWER7, 0, {RT}}, +{"mfgqr", XSPR(31,339,912), XSPRGQR_MASK, PPCPS, 0, {RT, SPRGQR}}, +{"mfhid2", XSPR(31,339,920), XSPR_MASK, GEKKO, 0, {RT}}, +{"mfwpar", XSPR(31,339,921), XSPR_MASK, GEKKO, 0, {RT}}, +{"mfdmau", XSPR(31,339,922), XSPR_MASK, GEKKO, 0, {RT}}, +{"mfdmal", XSPR(31,339,923), XSPR_MASK, GEKKO, 0, {RT}}, {"mfrstcfg", XSPR(31,339,923), XSPR_MASK, TITAN, 0, {RT}}, {"mfdcdbtrl", XSPR(31,339,924), XSPR_MASK, TITAN, 0, {RT}}, {"mfdcdbtrh", XSPR(31,339,925), XSPR_MASK, TITAN, 0, {RT}}, @@ -5983,10 +6034,15 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, 0, {RT}}, {"mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, 0, {RT}}, {"mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, 0, {RT}}, +{"mfhid0", XSPR(31,339,1008), XSPR_MASK, GEKKO, 0, {RT}}, +{"mfhid1", XSPR(31,339,1009), XSPR_MASK, GEKKO, 0, {RT}}, {"mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, 0, {RT}}, +{"mfiabr", XSPR(31,339,1010), XSPR_MASK, GEKKO, 0, {RT}}, +{"mfhid4", XSPR(31,339,1011), XSPR_MASK, BROADWAY, 0, {RT}}, {"mfdbdr", XSPR(31,339,1011), XSPR_MASK, TITAN, 0, {RS}}, {"mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, 0, {RT}}, {"mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, 0, {RT}}, +{"mfdabr", XSPR(31,339,1013), XSPR_MASK, PPC750, 0, {RT}}, {"mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, 0, {RT}}, {"mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, 0, {RT}}, {"mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, 0, {RT}}, @@ -6269,6 +6325,11 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"mtccr1", XSPR(31,467,888), XSPR_MASK, TITAN, 0, {RS}}, {"mtppr", XSPR(31,467,896), XSPR_MASK, POWER7, 0, {RS}}, {"mtppr32", XSPR(31,467,898), XSPR_MASK, POWER7, 0, {RS}}, +{"mtgqr", XSPR(31,467,912), XSPRGQR_MASK, PPCPS, 0, {SPRGQR, RS}}, +{"mthid2", XSPR(31,467,920), XSPR_MASK, GEKKO, 0, {RS}}, +{"mtwpar", XSPR(31,467,921), XSPR_MASK, GEKKO, 0, {RS}}, +{"mtdmau", XSPR(31,467,922), XSPR_MASK, GEKKO, 0, {RS}}, +{"mtdmal", XSPR(31,467,923), XSPR_MASK, GEKKO, 0, {RS}}, {"mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, 0, {RS}}, {"mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, 0, {RS}}, {"mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, 0, {RS}}, @@ -6309,10 +6370,15 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, 0, {RS}}, {"mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, 0, {RS}}, {"mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, 0, {RS}}, -{"mtdbdr", XSPR(31,467,1011), XSPR_MASK, TITAN, 0, {RS}}, +{"mthid0", XSPR(31,467,1008), XSPR_MASK, GEKKO, 0, {RS}}, +{"mthid1", XSPR(31,467,1009), XSPR_MASK, GEKKO, 0, {RS}}, {"mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, 0, {RS}}, +{"mtiabr", XSPR(31,467,1010), XSPR_MASK, GEKKO, 0, {RS}}, +{"mthid4", XSPR(31,467,1011), XSPR_MASK, BROADWAY, 0, {RS}}, +{"mtdbdr", XSPR(31,467,1011), XSPR_MASK, TITAN, 0, {RS}}, {"mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, 0, {RS}}, {"mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, 0, {RS}}, +{"mtdabr", XSPR(31,467,1013), XSPR_MASK, PPC750, 0, {RS}}, {"mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, 0, {RS}}, {"mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, 0, {RS}}, {"mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, 0, {RS}}, -- 2.30.2