From fa87544ca13000e62982d3005edb47a53401cfe7 Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Mon, 23 Sep 2019 11:56:47 +0000 Subject: [PATCH] Fix non-canonical CONST_INTs in altivec_copysign_v4sf3 (PR91823) The pattern was generating zero-extended rather than sign-extended CONST_INTs. 2019-09-23 Richard Sandiford gcc/ PR target/91823 * config/rs6000/altivec.md (altivec_copysign_v4sf3): Generate canonical CONST_INTs. Use gen_rtvec. From-SVN: r276055 --- gcc/ChangeLog | 6 ++++++ gcc/config/rs6000/altivec.md | 9 ++------- 2 files changed, 8 insertions(+), 7 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 9392b8f086f..30a55daad40 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2019-09-23 Richard Sandiford + + PR target/91823 + * config/rs6000/altivec.md (altivec_copysign_v4sf3): Generate + canonical CONST_INTs. Use gen_rtvec. + 2019-09-23 Richard Biener * tree-vect-loop.c (get_initial_def_for_reduction): Simplify, diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index 6fa4d80fc88..dc34528a4d5 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -2198,13 +2198,8 @@ "VECTOR_UNIT_ALTIVEC_P (V4SFmode)" { rtx mask = gen_reg_rtx (V4SImode); - rtvec v = rtvec_alloc (4); - unsigned HOST_WIDE_INT mask_val = ((unsigned HOST_WIDE_INT)1) << 31; - - RTVEC_ELT (v, 0) = GEN_INT (mask_val); - RTVEC_ELT (v, 1) = GEN_INT (mask_val); - RTVEC_ELT (v, 2) = GEN_INT (mask_val); - RTVEC_ELT (v, 3) = GEN_INT (mask_val); + rtx mask_val = gen_int_mode (HOST_WIDE_INT_1U << 31, SImode); + rtvec v = gen_rtvec (4, mask_val, mask_val, mask_val, mask_val); emit_insn (gen_vec_initv4sisi (mask, gen_rtx_PARALLEL (V4SImode, v))); emit_insn (gen_vector_select_v4sf (operands[0], operands[1], operands[2], -- 2.30.2