From fa913a2dc6aefabdb9c6e927ad7095e89ffe0211 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Fri, 20 Feb 2015 12:14:37 +0100 Subject: [PATCH] radeonsi: set PA_SU_HARDWARE_SCREEN_OFFSET to 0 MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit It was probably 0 already, but it doesn't hurt to set it. Reviewed-by: Michel Dänzer --- src/gallium/drivers/radeonsi/si_state.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 3eea0b6c18a..db8af210c6a 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -3122,6 +3122,8 @@ void si_init_config(struct si_context *sctx) si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF); si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA); + /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */ + si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0); si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000); si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000); si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0x00000000); -- 2.30.2