From fac813dc61e7298dfe9ee28295843a30eb253296 Mon Sep 17 00:00:00 2001 From: Rhys Perry Date: Fri, 17 Jul 2020 11:46:47 +0100 Subject: [PATCH] spirv: don't split memory barriers If the SPIR-V had a shared+image memory barrier, we would emit two NIR barriers: a shared barrier and an image barrier. Unlike a single barrier, two barriers allows transformations such as: intrinsic image_deref_store (ssa_27, ssa_33, ssa_34, ssa_32, ssa_25) (1) intrinsic memory_barrier_shared () () intrinsic memory_barrier_image () () intrinsic store_shared (ssa_35, ssa_24) (0, 1, 4, 0) -> intrinsic memory_barrier_shared () () intrinsic store_shared (ssa_35, ssa_24) (0, 1, 4, 0) intrinsic image_deref_store (ssa_27, ssa_33, ssa_34, ssa_32, ssa_25) (1) intrinsic memory_barrier_image () () This commit fixes two dEQP-VK.memory_model.* CTS tests with ACO. Signed-off-by: Rhys Perry Reviewed-by: Caio Marcelo de Oliveira Filho Part-of: --- .gitlab-ci/deqp-radv-navi10-aco-fails.txt | 2 - .gitlab-ci/deqp-radv-navi14-aco-fails.txt | 2 - .gitlab-ci/deqp-radv-pitcairn-aco-fails.txt | 2 - .gitlab-ci/deqp-radv-raven-aco-fails.txt | 2 - src/compiler/spirv/spirv_to_nir.c | 69 +++++++++++---------- 5 files changed, 36 insertions(+), 41 deletions(-) diff --git a/.gitlab-ci/deqp-radv-navi10-aco-fails.txt b/.gitlab-ci/deqp-radv-navi10-aco-fails.txt index d5e9453b0c5..1f4a94c4d9c 100644 --- a/.gitlab-ci/deqp-radv-navi10-aco-fails.txt +++ b/.gitlab-ci/deqp-radv-navi10-aco-fails.txt @@ -2,8 +2,6 @@ dEQP-VK.transform_feedback.simple.multistreams_1 dEQP-VK.transform_feedback.simple.multistreams_3 -dEQP-VK.memory_model.message_passing.core11.u32.coherent.fence_fence.atomicwrite.device.payload_local.image.guard_nonlocal.workgroup.comp -dEQP-VK.memory_model.message_passing.core11.u32.coherent.fence_fence.atomicwrite.device.payload_nonlocal.image.guard_nonlocal.workgroup.comp dEQP-VK.rasterization.flatshading.line_strip_wide dEQP-VK.rasterization.flatshading.non_strict_line_strip_wide dEQP-VK.rasterization.flatshading.non_strict_lines_wide diff --git a/.gitlab-ci/deqp-radv-navi14-aco-fails.txt b/.gitlab-ci/deqp-radv-navi14-aco-fails.txt index d5e9453b0c5..1f4a94c4d9c 100644 --- a/.gitlab-ci/deqp-radv-navi14-aco-fails.txt +++ b/.gitlab-ci/deqp-radv-navi14-aco-fails.txt @@ -2,8 +2,6 @@ dEQP-VK.transform_feedback.simple.multistreams_1 dEQP-VK.transform_feedback.simple.multistreams_3 -dEQP-VK.memory_model.message_passing.core11.u32.coherent.fence_fence.atomicwrite.device.payload_local.image.guard_nonlocal.workgroup.comp -dEQP-VK.memory_model.message_passing.core11.u32.coherent.fence_fence.atomicwrite.device.payload_nonlocal.image.guard_nonlocal.workgroup.comp dEQP-VK.rasterization.flatshading.line_strip_wide dEQP-VK.rasterization.flatshading.non_strict_line_strip_wide dEQP-VK.rasterization.flatshading.non_strict_lines_wide diff --git a/.gitlab-ci/deqp-radv-pitcairn-aco-fails.txt b/.gitlab-ci/deqp-radv-pitcairn-aco-fails.txt index dd37cbc223a..5ec617dcae7 100644 --- a/.gitlab-ci/deqp-radv-pitcairn-aco-fails.txt +++ b/.gitlab-ci/deqp-radv-pitcairn-aco-fails.txt @@ -1,5 +1,3 @@ -dEQP-VK.memory_model.message_passing.core11.u32.coherent.fence_fence.atomicwrite.device.payload_local.image.guard_nonlocal.workgroup.comp -dEQP-VK.memory_model.message_passing.core11.u32.coherent.fence_fence.atomicwrite.device.payload_nonlocal.image.guard_nonlocal.workgroup.comp dEQP-VK.pipeline.depth.format.d16_unorm.compare_ops.never_zerodepthbounds_depthdisabled_stencilenabled dEQP-VK.pipeline.depth.format.d32_sfloat.compare_ops.never_zerodepthbounds_depthdisabled_stencilenabled dEQP-VK.rasterization.flatshading.line_strip_wide diff --git a/.gitlab-ci/deqp-radv-raven-aco-fails.txt b/.gitlab-ci/deqp-radv-raven-aco-fails.txt index d5e9453b0c5..1f4a94c4d9c 100644 --- a/.gitlab-ci/deqp-radv-raven-aco-fails.txt +++ b/.gitlab-ci/deqp-radv-raven-aco-fails.txt @@ -2,8 +2,6 @@ dEQP-VK.transform_feedback.simple.multistreams_1 dEQP-VK.transform_feedback.simple.multistreams_3 -dEQP-VK.memory_model.message_passing.core11.u32.coherent.fence_fence.atomicwrite.device.payload_local.image.guard_nonlocal.workgroup.comp -dEQP-VK.memory_model.message_passing.core11.u32.coherent.fence_fence.atomicwrite.device.payload_nonlocal.image.guard_nonlocal.workgroup.comp dEQP-VK.rasterization.flatshading.line_strip_wide dEQP-VK.rasterization.flatshading.non_strict_line_strip_wide dEQP-VK.rasterization.flatshading.non_strict_lines_wide diff --git a/src/compiler/spirv/spirv_to_nir.c b/src/compiler/spirv/spirv_to_nir.c index b9f35ad0262..e98728396fc 100644 --- a/src/compiler/spirv/spirv_to_nir.c +++ b/src/compiler/spirv/spirv_to_nir.c @@ -3578,40 +3578,43 @@ vtn_emit_memory_barrier(struct vtn_builder *b, SpvScope scope, /* There's only two scopes thing left */ vtn_assert(scope == SpvScopeInvocation || scope == SpvScopeDevice); - /* Map the GLSL memoryBarrier() construct to the corresponding NIR one. */ - static const SpvMemorySemanticsMask glsl_memory_barrier = - SpvMemorySemanticsUniformMemoryMask | - SpvMemorySemanticsWorkgroupMemoryMask | - SpvMemorySemanticsImageMemoryMask; - if ((semantics & glsl_memory_barrier) == glsl_memory_barrier) { - vtn_emit_barrier(b, nir_intrinsic_memory_barrier); - semantics &= ~(glsl_memory_barrier | SpvMemorySemanticsAtomicCounterMemoryMask); - } - - /* Issue a bunch of more specific barriers */ - uint32_t bits = semantics; - while (bits) { - SpvMemorySemanticsMask semantic = 1 << u_bit_scan(&bits); - switch (semantic) { - case SpvMemorySemanticsUniformMemoryMask: - vtn_emit_barrier(b, nir_intrinsic_memory_barrier_buffer); - break; - case SpvMemorySemanticsWorkgroupMemoryMask: - vtn_emit_barrier(b, nir_intrinsic_memory_barrier_shared); - break; - case SpvMemorySemanticsAtomicCounterMemoryMask: - vtn_emit_barrier(b, nir_intrinsic_memory_barrier_atomic_counter); - break; - case SpvMemorySemanticsImageMemoryMask: - vtn_emit_barrier(b, nir_intrinsic_memory_barrier_image); - break; - case SpvMemorySemanticsOutputMemoryMask: - if (b->nb.shader->info.stage == MESA_SHADER_TESS_CTRL) - vtn_emit_barrier(b, nir_intrinsic_memory_barrier_tcs_patch); - break; - default: - break;; + /* Map the GLSL memoryBarrier() construct and any barriers with more than one + * semantic to the corresponding NIR one. + */ + if (util_bitcount(semantics & all_memory_semantics) > 1) { + vtn_emit_barrier(b, nir_intrinsic_memory_barrier); + if (semantics & SpvMemorySemanticsOutputMemoryMask) { + /* GLSL memoryBarrier() (and the corresponding NIR one) doesn't include + * TCS outputs, so we have to emit it's own intrinsic for that. We + * then need to emit another memory_barrier to prevent moving + * non-output operations to before the tcs_patch barrier. + */ + vtn_emit_barrier(b, nir_intrinsic_memory_barrier_tcs_patch); + vtn_emit_barrier(b, nir_intrinsic_memory_barrier); } + return; + } + + /* Issue a more specific barrier */ + switch (semantics & all_memory_semantics) { + case SpvMemorySemanticsUniformMemoryMask: + vtn_emit_barrier(b, nir_intrinsic_memory_barrier_buffer); + break; + case SpvMemorySemanticsWorkgroupMemoryMask: + vtn_emit_barrier(b, nir_intrinsic_memory_barrier_shared); + break; + case SpvMemorySemanticsAtomicCounterMemoryMask: + vtn_emit_barrier(b, nir_intrinsic_memory_barrier_atomic_counter); + break; + case SpvMemorySemanticsImageMemoryMask: + vtn_emit_barrier(b, nir_intrinsic_memory_barrier_image); + break; + case SpvMemorySemanticsOutputMemoryMask: + if (b->nb.shader->info.stage == MESA_SHADER_TESS_CTRL) + vtn_emit_barrier(b, nir_intrinsic_memory_barrier_tcs_patch); + break; + default: + break; } } -- 2.30.2