From fac921db63c74c543aad090929187960fadeefa5 Mon Sep 17 00:00:00 2001 From: Karol Herbst Date: Tue, 21 Mar 2017 18:37:46 +0100 Subject: [PATCH] nvc0/ir: disable support for LIMMs on MAD/FMA I hit an assert in the emiter while toying around with optimizations, because ConstantFolding immediated a big int into a mad. There is special handling for FMA/MAD in insnCanLoad, which is broken. With this patch the special path should be not hit anymore. Anyway, the constraints for the LIMMS can't be guarenteed in SSA form and I have patches pending to use it via a post-SSA optimization pass. As a result, immediates get immediated for int mad/fmas as well. changes in shader-db: total instructions in shared programs : 3943335 -> 3941587 (-0.04%) total gprs used in shared programs : 481563 -> 481511 (-0.01%) total local used in shared programs : 27469 -> 27469 (0.00%) total bytes used in shared programs : 36139384 -> 36123344 (-0.04%) Signed-off-by: Karol Herbst [imirkin: remove extra bit from insnCanLoad as well] Reviewed-by: Ilia Mirkin --- .../drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp index 1d2e4c3c090..0df528f60cb 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp @@ -104,8 +104,8 @@ static const struct opProperties _initProps[] = { OP_MUL, 0x3, 0x0, 0x0, 0x8, 0x2, 0x2 | 0x8 }, { OP_MAX, 0x3, 0x3, 0x0, 0x0, 0x2, 0x2 }, { OP_MIN, 0x3, 0x3, 0x0, 0x0, 0x2, 0x2 }, - { OP_MAD, 0x7, 0x0, 0x0, 0x8, 0x6, 0x2 | 0x8 }, // special c[] constraint - { OP_FMA, 0x7, 0x0, 0x0, 0x8, 0x6, 0x2 | 0x8 }, // keep the same as OP_MAD + { OP_MAD, 0x7, 0x0, 0x0, 0x8, 0x6, 0x2 }, // special c[] constraint + { OP_FMA, 0x7, 0x0, 0x0, 0x8, 0x6, 0x2 }, // keep the same as OP_MAD { OP_SHLADD, 0x5, 0x0, 0x0, 0x0, 0x4, 0x6 }, { OP_MADSP, 0x0, 0x0, 0x0, 0x0, 0x6, 0x2 }, { OP_ABS, 0x0, 0x0, 0x0, 0x0, 0x1, 0x0 }, @@ -381,12 +381,6 @@ TargetNVC0::insnCanLoad(const Instruction *i, int s, return false; } } else - if (i->op == OP_MAD || i->op == OP_FMA) { - // requires src == dst, cannot decide before RA - // (except if we implement more constraints) - if (ld->getSrc(0)->asImm()->reg.data.u32 & 0xfff) - return false; - } else if (i->op == OP_ADD && i->sType == TYPE_F32) { // add f32 LIMM cannot saturate if (i->saturate && (reg.data.u32 & 0xfff)) -- 2.30.2