From fad3cd5f00155f88148c608d3abe85e25c416a11 Mon Sep 17 00:00:00 2001 From: Cesar Strauss Date: Sat, 3 Apr 2021 15:21:37 -0300 Subject: [PATCH] Signal the simulator when completing a VL loop When we reach the end of the VL loop, by skipping masked bits in the predicate, we still need to synchronize with the Simulator, even if no instruction was issued. --- src/soc/simple/issuer.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py index 8d9bec5e..075655f1 100644 --- a/src/soc/simple/issuer.py +++ b/src/soc/simple/issuer.py @@ -628,6 +628,8 @@ class TestIssuerInternal(Elaboratable): comb += new_svstate.srcstep.eq(0) comb += new_svstate.dststep.eq(0) comb += update_svstate.eq(1) + # synchronize with the simulator + comb += self.insn_done.eq(1) # go back to Issue m.next = "ISSUE_START" with m.Else(): -- 2.30.2