From faf0d9a21c9547be7fd3f690b924037ddc4b69ee Mon Sep 17 00:00:00 2001 From: lkcl Date: Wed, 27 Apr 2022 12:48:45 +0100 Subject: [PATCH] --- openpower/sv/biginteger/analysis.mdwn | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/openpower/sv/biginteger/analysis.mdwn b/openpower/sv/biginteger/analysis.mdwn index 2583d7941..1d8fe9dc2 100644 --- a/openpower/sv/biginteger/analysis.mdwn +++ b/openpower/sv/biginteger/analysis.mdwn @@ -384,7 +384,8 @@ simply does not exist in most Scalar 64-bit ISAs. Although Power ISA comes close with `divdeu`, by placing the dividend in the upper half of a 128-bit computation, the lower half is zero. Again Power ISA has a Packed SIMD instruction `vdivuq` which is a 128/128 -(quad) divide, not a 128/64. Some investigation into +(quad) divide, not a 128/64, and its use would require considerable +effort to move registers to and from GPRs. Some investigation into soft-implementations of 128/128 or 128/64 divide show it to be typically implemented bit-wise, with all that implies. -- 2.30.2