From fafe81deaabb98e055483b9cb78ad9b43ab43c1e Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Wed, 20 Sep 2023 15:22:06 -0700 Subject: [PATCH] Revert "fix PowerDecoder2 to properly decode scalar EXTRA2" Luke wants all changes to EXTRA2/3 decoding to be in one commit, restore to original state This reverts commit 630dfa6c8b6633d66d1a41368dfad927754846ed. --- src/openpower/decoder/power_svp64_extra.py | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/src/openpower/decoder/power_svp64_extra.py b/src/openpower/decoder/power_svp64_extra.py index 620f0660..c956eb99 100644 --- a/src/openpower/decoder/power_svp64_extra.py +++ b/src/openpower/decoder/power_svp64_extra.py @@ -105,11 +105,8 @@ class SVP64RegExtra(SVP64ExtraSpec): with m.If(self.isvec): # Vector: shifted up, extra in LSBs (RA << 2) | spec[1:2] comb += self.reg_out.eq(Cat(spec_aug, self.reg_in)) - with m.Elif(self.etype == SVEType.EXTRA2): - # Scalar EXTRA2: not shifted up, extra in MSBs RA | (spec[1] << 5) - comb += self.reg_out.eq(Cat(self.reg_in, spec_aug[1])) - with m.Elif(self.etype == SVEType.EXTRA3): - # Scalar EXTRA3: not shifted up, extra in MSBs RA | (spec[1:2] << 5) + with m.Else(): + # Scalar: not shifted up, extra in MSBs RA | (spec[1:2] << 5) comb += self.reg_out.eq(Cat(self.reg_in, spec_aug)) return m -- 2.30.2