From fb055f4b745b1b56d84ad920508ebed2d22d3616 Mon Sep 17 00:00:00 2001 From: "H.J. Lu" Date: Thu, 14 Mar 2019 08:49:54 +0000 Subject: [PATCH] x32: Add addr32 prefix to VSIB address 32-bit indices in VSIB address are sign-extended to 64 bits. In x32, when 32-bit indices are used as addresses, like in vgatherdps %ymm7, 0(,%ymm9,1), %ymm6 32-bit indices, 0xf7fa3010, is sign-extended to 0xfffffffff7fa3010 which is invalid address. Add addr32 prefix to UNSPEC_VSIBADDR instructions for x32 if there is no base register nor symbol. This fixes 175.vpr and 254.gap in SPEC CPU 2000 on x32 with -Ofast -funroll-loops -march=haswell gcc/ PR target/89523 * config/i386/i386.c (ix86_print_operand): Handle 'M' to add addr32 prefix to VSIB address for X32. * config/i386/sse.md (*avx512pf_gatherpfsf_mask): Prepend "%M2" to opcode. (*avx512pf_gatherpfdf_mask): Likewise. (*avx512pf_scatterpfsf_mask): Likewise. (*avx512pf_scatterpfdf_mask): Likewise. (*avx2_gathersi): Prepend "%M3" to opcode. (*avx2_gathersi_2): Prepend "%M2" to opcode. (*avx2_gatherdi): Prepend "%M3" to opcode. (*avx2_gatherdi_2): Prepend "%M2" to opcode. (*avx2_gatherdi_3): Prepend "%M3" to opcode. (*avx2_gatherdi_4): Prepend "%M2" to opcode.` (*avx512f_gathersi): Prepend "%M4" to opcode. (*avx512f_gathersi_2): Prepend "%M3" to opcode. (*avx512f_gatherdi): Prepend "%M4" to opcode. (*avx512f_gatherdi_2): Prepend "%M3" to opcode. (*avx512f_scattersi): Prepend "%M0" to opcode. (*avx512f_scatterdi): Likewise. gcc/testsuite/ PR target/89523 * gcc.target/i386/pr89523-1a.c: New test. * gcc.target/i386/pr89523-1b.c: Likewise. * gcc.target/i386/pr89523-2.c: Likewise. * gcc.target/i386/pr89523-3.c: Likewise. * gcc.target/i386/pr89523-4.c: Likewise. * gcc.target/i386/pr89523-5.c: Likewise. * gcc.target/i386/pr89523-6.c: Likewise. * gcc.target/i386/pr89523-7.c: Likewise. * gcc.target/i386/pr89523-8.c: Likewise. * gcc.target/i386/pr89523-9.c: Likewise. From-SVN: r269673 --- gcc/ChangeLog | 23 +++++++++++ gcc/config/i386/i386.c | 21 ++++++++++ gcc/config/i386/sse.md | 46 +++++++++++----------- gcc/testsuite/ChangeLog | 14 +++++++ gcc/testsuite/gcc.target/i386/pr89523-1a.c | 24 +++++++++++ gcc/testsuite/gcc.target/i386/pr89523-1b.c | 7 ++++ gcc/testsuite/gcc.target/i386/pr89523-2.c | 37 +++++++++++++++++ gcc/testsuite/gcc.target/i386/pr89523-3.c | 36 +++++++++++++++++ gcc/testsuite/gcc.target/i386/pr89523-4.c | 36 +++++++++++++++++ gcc/testsuite/gcc.target/i386/pr89523-5.c | 39 ++++++++++++++++++ gcc/testsuite/gcc.target/i386/pr89523-6.c | 38 ++++++++++++++++++ gcc/testsuite/gcc.target/i386/pr89523-7.c | 42 ++++++++++++++++++++ gcc/testsuite/gcc.target/i386/pr89523-8.c | 41 +++++++++++++++++++ gcc/testsuite/gcc.target/i386/pr89523-9.c | 30 ++++++++++++++ 14 files changed, 411 insertions(+), 23 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/pr89523-1a.c create mode 100644 gcc/testsuite/gcc.target/i386/pr89523-1b.c create mode 100644 gcc/testsuite/gcc.target/i386/pr89523-2.c create mode 100644 gcc/testsuite/gcc.target/i386/pr89523-3.c create mode 100644 gcc/testsuite/gcc.target/i386/pr89523-4.c create mode 100644 gcc/testsuite/gcc.target/i386/pr89523-5.c create mode 100644 gcc/testsuite/gcc.target/i386/pr89523-6.c create mode 100644 gcc/testsuite/gcc.target/i386/pr89523-7.c create mode 100644 gcc/testsuite/gcc.target/i386/pr89523-8.c create mode 100644 gcc/testsuite/gcc.target/i386/pr89523-9.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index baed65f898b..927fd9e4be5 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,26 @@ +2019-03-14 H.J. Lu + + PR target/89523 + * config/i386/i386.c (ix86_print_operand): Handle 'M' to add + addr32 prefix to VSIB address for X32. + * config/i386/sse.md (*avx512pf_gatherpfsf_mask): Prepend + "%M2" to opcode. + (*avx512pf_gatherpfdf_mask): Likewise. + (*avx512pf_scatterpfsf_mask): Likewise. + (*avx512pf_scatterpfdf_mask): Likewise. + (*avx2_gathersi): Prepend "%M3" to opcode. + (*avx2_gathersi_2): Prepend "%M2" to opcode. + (*avx2_gatherdi): Prepend "%M3" to opcode. + (*avx2_gatherdi_2): Prepend "%M2" to opcode. + (*avx2_gatherdi_3): Prepend "%M3" to opcode. + (*avx2_gatherdi_4): Prepend "%M2" to opcode.` + (*avx512f_gathersi): Prepend "%M4" to opcode. + (*avx512f_gathersi_2): Prepend "%M3" to opcode. + (*avx512f_gatherdi): Prepend "%M4" to opcode. + (*avx512f_gatherdi_2): Prepend "%M3" to opcode. + (*avx512f_scattersi): Prepend "%M0" to opcode. + (*avx512f_scatterdi): Likewise. + 2019-03-13 Vladimir Makarov PR target/85860 diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index fe459071aaf..1f94a45909d 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -17813,6 +17813,7 @@ print_reg (rtx x, int code, FILE *file) ; -- print a semicolon (after prefixes due to bug in older gas). ~ -- print "i" if TARGET_AVX2, "f" otherwise. ^ -- print addr32 prefix if TARGET_64BIT and Pmode != word_mode + M -- print addr32 prefix for TARGET_X32 with VSIB address. ! -- print NOTRACK prefix for jxx/call/ret instructions if required. */ @@ -18360,6 +18361,26 @@ ix86_print_operand (FILE *file, rtx x, int code) putc (TARGET_AVX2 ? 'i' : 'f', file); return; + case 'M': + if (TARGET_X32) + { + /* NB: 32-bit indices in VSIB address are sign-extended + to 64 bits. In x32, if 32-bit address 0xf7fa3010 is + sign-extended to 0xfffffffff7fa3010 which is invalid + address. Add addr32 prefix if there is no base + register nor symbol. */ + bool ok; + struct ix86_address parts; + ok = ix86_decompose_address (x, &parts); + gcc_assert (ok && parts.index == NULL_RTX); + if (parts.base == NULL_RTX + && (parts.disp == NULL_RTX + || !symbolic_operand (parts.disp, + GET_MODE (parts.disp)))) + fputs ("addr32 ", file); + } + return; + case '^': if (TARGET_64BIT && Pmode != word_mode) fputs ("addr32 ", file); diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index d4c01407f4a..86bf8661808 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -17486,9 +17486,9 @@ case 3: /* %X5 so that we don't emit any *WORD PTR for -masm=intel, as gas changed what it requires incompatibly. */ - return "vgatherpf0ps\t{%5%{%0%}|%X5%{%0%}}"; + return "%M2vgatherpf0ps\t{%5%{%0%}|%X5%{%0%}}"; case 2: - return "vgatherpf1ps\t{%5%{%0%}|%X5%{%0%}}"; + return "%M2vgatherpf1ps\t{%5%{%0%}|%X5%{%0%}}"; default: gcc_unreachable (); } @@ -17533,9 +17533,9 @@ case 3: /* %X5 so that we don't emit any *WORD PTR for -masm=intel, as gas changed what it requires incompatibly. */ - return "vgatherpf0pd\t{%5%{%0%}|%X5%{%0%}}"; + return "%M2vgatherpf0pd\t{%5%{%0%}|%X5%{%0%}}"; case 2: - return "vgatherpf1pd\t{%5%{%0%}|%X5%{%0%}}"; + return "%M2vgatherpf1pd\t{%5%{%0%}|%X5%{%0%}}"; default: gcc_unreachable (); } @@ -17581,10 +17581,10 @@ case 7: /* %X5 so that we don't emit any *WORD PTR for -masm=intel, as gas changed what it requires incompatibly. */ - return "vscatterpf0ps\t{%5%{%0%}|%X5%{%0%}}"; + return "%M2vscatterpf0ps\t{%5%{%0%}|%X5%{%0%}}"; case 2: case 6: - return "vscatterpf1ps\t{%5%{%0%}|%X5%{%0%}}"; + return "%M2vscatterpf1ps\t{%5%{%0%}|%X5%{%0%}}"; default: gcc_unreachable (); } @@ -17630,10 +17630,10 @@ case 7: /* %X5 so that we don't emit any *WORD PTR for -masm=intel, as gas changed what it requires incompatibly. */ - return "vscatterpf0pd\t{%5%{%0%}|%X5%{%0%}}"; + return "%M2vscatterpf0pd\t{%5%{%0%}|%X5%{%0%}}"; case 2: case 6: - return "vscatterpf1pd\t{%5%{%0%}|%X5%{%0%}}"; + return "%M2vscatterpf1pd\t{%5%{%0%}|%X5%{%0%}}"; default: gcc_unreachable (); } @@ -20377,7 +20377,7 @@ UNSPEC_GATHER)) (clobber (match_scratch:VEC_GATHER_MODE 1 "=&x"))] "TARGET_AVX2" - "vgatherd\t{%1, %7, %0|%0, %7, %1}" + "%M3vgatherd\t{%1, %7, %0|%0, %7, %1}" [(set_attr "type" "ssemov") (set_attr "prefix" "vex") (set_attr "mode" "")]) @@ -20397,7 +20397,7 @@ UNSPEC_GATHER)) (clobber (match_scratch:VEC_GATHER_MODE 1 "=&x"))] "TARGET_AVX2" - "vgatherd\t{%1, %6, %0|%0, %6, %1}" + "%M2vgatherd\t{%1, %6, %0|%0, %6, %1}" [(set_attr "type" "ssemov") (set_attr "prefix" "vex") (set_attr "mode" "")]) @@ -20438,7 +20438,7 @@ UNSPEC_GATHER)) (clobber (match_scratch:VEC_GATHER_MODE 1 "=&x"))] "TARGET_AVX2" - "vgatherq\t{%5, %7, %2|%2, %7, %5}" + "%M3vgatherq\t{%5, %7, %2|%2, %7, %5}" [(set_attr "type" "ssemov") (set_attr "prefix" "vex") (set_attr "mode" "")]) @@ -20460,8 +20460,8 @@ "TARGET_AVX2" { if (mode != mode) - return "vgatherq\t{%4, %6, %x0|%x0, %6, %4}"; - return "vgatherq\t{%4, %6, %0|%0, %6, %4}"; + return "%M2vgatherq\t{%4, %6, %x0|%x0, %6, %4}"; + return "%M2vgatherq\t{%4, %6, %0|%0, %6, %4}"; } [(set_attr "type" "ssemov") (set_attr "prefix" "vex") @@ -20485,7 +20485,7 @@ (const_int 2) (const_int 3)]))) (clobber (match_scratch:VI4F_256 1 "=&x"))] "TARGET_AVX2" - "vgatherq\t{%5, %7, %0|%0, %7, %5}" + "%M3vgatherq\t{%5, %7, %0|%0, %7, %5}" [(set_attr "type" "ssemov") (set_attr "prefix" "vex") (set_attr "mode" "")]) @@ -20508,7 +20508,7 @@ (const_int 2) (const_int 3)]))) (clobber (match_scratch:VI4F_256 1 "=&x"))] "TARGET_AVX2" - "vgatherq\t{%4, %6, %0|%0, %6, %4}" + "%M2vgatherq\t{%4, %6, %0|%0, %6, %4}" [(set_attr "type" "ssemov") (set_attr "prefix" "vex") (set_attr "mode" "")]) @@ -20548,7 +20548,7 @@ "TARGET_AVX512F" ;; %X6 so that we don't emit any *WORD PTR for -masm=intel, as ;; gas changed what it requires incompatibly. - "vgatherd\t{%6, %0%{%2%}|%0%{%2%}, %X6}" + "%M4vgatherd\t{%6, %0%{%2%}|%0%{%2%}, %X6}" [(set_attr "type" "ssemov") (set_attr "prefix" "evex") (set_attr "mode" "")]) @@ -20569,7 +20569,7 @@ "TARGET_AVX512F" ;; %X5 so that we don't emit any *WORD PTR for -masm=intel, as ;; gas changed what it requires incompatibly. - "vgatherd\t{%5, %0%{%1%}|%0%{%1%}, %X5}" + "%M3vgatherd\t{%5, %0%{%1%}|%0%{%1%}, %X5}" [(set_attr "type" "ssemov") (set_attr "prefix" "evex") (set_attr "mode" "")]) @@ -20610,7 +20610,7 @@ "TARGET_AVX512F" ;; %X6 so that we don't emit any *WORD PTR for -masm=intel, as ;; gas changed what it requires incompatibly. - "vgatherq\t{%6, %1%{%2%}|%1%{%2%}, %X6}" + "%M4vgatherq\t{%6, %1%{%2%}|%1%{%2%}, %X6}" [(set_attr "type" "ssemov") (set_attr "prefix" "evex") (set_attr "mode" "")]) @@ -20635,11 +20635,11 @@ if (mode != mode) { if ( != 64) - return "vgatherq\t{%5, %x0%{%1%}|%x0%{%1%}, %X5}"; + return "%M3vgatherq\t{%5, %x0%{%1%}|%x0%{%1%}, %X5}"; else - return "vgatherq\t{%5, %t0%{%1%}|%t0%{%1%}, %X5}"; + return "%M3vgatherq\t{%5, %t0%{%1%}|%t0%{%1%}, %X5}"; } - return "vgatherq\t{%5, %0%{%1%}|%0%{%1%}, %X5}"; + return "%M3vgatherq\t{%5, %0%{%1%}|%0%{%1%}, %X5}"; } [(set_attr "type" "ssemov") (set_attr "prefix" "evex") @@ -20678,7 +20678,7 @@ "TARGET_AVX512F" ;; %X5 so that we don't emit any *WORD PTR for -masm=intel, as ;; gas changed what it requires incompatibly. - "vscatterd\t{%3, %5%{%1%}|%X5%{%1%}, %3}" + "%M0vscatterd\t{%3, %5%{%1%}|%X5%{%1%}, %3}" [(set_attr "type" "ssemov") (set_attr "prefix" "evex") (set_attr "mode" "")]) @@ -20716,7 +20716,7 @@ "TARGET_AVX512F" ;; %X5 so that we don't emit any *WORD PTR for -masm=intel, as ;; gas changed what it requires incompatibly. - "vscatterq\t{%3, %5%{%1%}|%X5%{%1%}, %3}" + "%M0vscatterq\t{%3, %5%{%1%}|%X5%{%1%}, %3}" [(set_attr "type" "ssemov") (set_attr "prefix" "evex") (set_attr "mode" "")]) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index dbd918c6ca4..0776c676196 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,17 @@ +2019-03-14 H.J. Lu + + PR target/89523 + * gcc.target/i386/pr89523-1a.c: New test. + * gcc.target/i386/pr89523-1b.c: Likewise. + * gcc.target/i386/pr89523-2.c: Likewise. + * gcc.target/i386/pr89523-3.c: Likewise. + * gcc.target/i386/pr89523-4.c: Likewise. + * gcc.target/i386/pr89523-5.c: Likewise. + * gcc.target/i386/pr89523-6.c: Likewise. + * gcc.target/i386/pr89523-7.c: Likewise. + * gcc.target/i386/pr89523-8.c: Likewise. + * gcc.target/i386/pr89523-9.c: Likewise. + 2019-03-14 Jakub Jelinek PR c++/89512 diff --git a/gcc/testsuite/gcc.target/i386/pr89523-1a.c b/gcc/testsuite/gcc.target/i386/pr89523-1a.c new file mode 100644 index 00000000000..0d0edab0363 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr89523-1a.c @@ -0,0 +1,24 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-require-effective-target maybe_x32 } */ +/* { dg-options "-maddress-mode=short -mx32 -Ofast -funroll-loops -march=haswell" } */ +/* { dg-final { scan-assembler-not "\tvgather" } } */ +/* { dg-final { scan-assembler "addr32 vgather" } } */ + +void foo (void); + +extern float *ncost; + +float +bar (int type, int num) +{ + int i; + float cost; + + cost = 0; + for (i = 0; i < num; i++) + if (type) + cost += ncost[i]; + else + foo (); + return (cost); +} diff --git a/gcc/testsuite/gcc.target/i386/pr89523-1b.c b/gcc/testsuite/gcc.target/i386/pr89523-1b.c new file mode 100644 index 00000000000..6a5c1d43625 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr89523-1b.c @@ -0,0 +1,7 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-require-effective-target maybe_x32 } */ +/* { dg-options "-maddress-mode=long -mx32 -Ofast -funroll-loops -march=haswell" } */ +/* { dg-final { scan-assembler-not "\tvgather" } } */ +/* { dg-final { scan-assembler "addr32 vgather" } } */ + +#include "pr89523-1a.c" diff --git a/gcc/testsuite/gcc.target/i386/pr89523-2.c b/gcc/testsuite/gcc.target/i386/pr89523-2.c new file mode 100644 index 00000000000..2ffbffe5e40 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr89523-2.c @@ -0,0 +1,37 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-require-effective-target maybe_x32 } */ +/* { dg-options "-mx32 -O2 -march=haswell" } */ +/* { dg-final { scan-assembler "\tvgather" } } */ +/* { dg-final { scan-assembler-not "addr32 vgather" } } */ + +typedef double __v2df __attribute__ ((__vector_size__ (16))); +typedef int __v4si __attribute__ ((__vector_size__ (16))); +typedef long long __v2di __attribute__ ((__vector_size__ (16))); + +typedef long long __m128i __attribute__ ((__vector_size__ (16), __may_alias__)); +typedef double __m128d __attribute__ ((__vector_size__ (16), __may_alias__)); + +extern __inline __m128d +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm_i32gather_pd (double const *__base, __m128i __index, const int __scale) +{ + __v2df __zero = { 0.0, 0.0 }; + __v2df __mask = __builtin_ia32_cmpeqpd (__zero, __zero); + __v2df x = x; + + return (__m128d) __builtin_ia32_gathersiv2df (x, + __base, + (__v4si)__index, + __mask, + __scale); +} + +__m128d x; +double *base; +__m128i idx; + +void extern +avx2_test (void) +{ + x = _mm_i32gather_pd (base, idx, 1); +} diff --git a/gcc/testsuite/gcc.target/i386/pr89523-3.c b/gcc/testsuite/gcc.target/i386/pr89523-3.c new file mode 100644 index 00000000000..fc3631b694b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr89523-3.c @@ -0,0 +1,36 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-require-effective-target maybe_x32 } */ +/* { dg-options "-mx32 -O2 -march=haswell" } */ +/* { dg-final { scan-assembler "\tvgather" } } */ +/* { dg-final { scan-assembler-not "addr32 vgather" } } */ + +typedef double __v2df __attribute__ ((__vector_size__ (16))); +typedef int __v4si __attribute__ ((__vector_size__ (16))); +typedef long long __v2di __attribute__ ((__vector_size__ (16))); + +typedef long long __m128i __attribute__ ((__vector_size__ (16), __may_alias__)); +typedef double __m128d __attribute__ ((__vector_size__ (16), __may_alias__)); + +extern __inline __m128d +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm_i64gather_pd (double const *__base, __m128i __index, const int __scale) +{ + __v2df __zero = { 0.0, 0.0 }; + __v2df __mask = __builtin_ia32_cmpeqpd (__zero, __zero); + + return (__m128d) __builtin_ia32_gatherdiv2df (__zero, + __base, + (__v2di)__index, + __mask, + __scale); +} + +__m128d x; +double *base; +__m128i idx; + +void extern +avx2_test (void) +{ + x = _mm_i64gather_pd (base, idx, 1); +} diff --git a/gcc/testsuite/gcc.target/i386/pr89523-4.c b/gcc/testsuite/gcc.target/i386/pr89523-4.c new file mode 100644 index 00000000000..3436e5dcae3 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr89523-4.c @@ -0,0 +1,36 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-require-effective-target maybe_x32 } */ +/* { dg-options "-mx32 -O2 -march=haswell" } */ +/* { dg-final { scan-assembler-not "\tvgather" } } */ +/* { dg-final { scan-assembler "addr32 vgather" } } */ + +typedef double __v2df __attribute__ ((__vector_size__ (16))); +typedef int __v4si __attribute__ ((__vector_size__ (16))); +typedef long long __v2di __attribute__ ((__vector_size__ (16))); + +typedef long long __m128i __attribute__ ((__vector_size__ (16), __may_alias__)); +typedef double __m128d __attribute__ ((__vector_size__ (16), __may_alias__)); + +extern __inline __m128d +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm_i32gather_pd (double const *__base, __m128i __index, const int __scale) +{ + __v2df __zero = { 0.0, 0.0 }; + __v2df __mask = __builtin_ia32_cmpeqpd (__zero, __zero); + __v2df x = x; + + return (__m128d) __builtin_ia32_gathersiv2df (x, + __base, + (__v4si)__index, + __mask, + __scale); +} + +__m128d x; +__m128i idx; + +void extern +avx2_test (void) +{ + x = _mm_i32gather_pd ((void *) 0, idx, 1); +} diff --git a/gcc/testsuite/gcc.target/i386/pr89523-5.c b/gcc/testsuite/gcc.target/i386/pr89523-5.c new file mode 100644 index 00000000000..6a769c7a249 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr89523-5.c @@ -0,0 +1,39 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-require-effective-target maybe_x32 } */ +/* { dg-options "-mx32 -O2 -mavx512pf" } */ +/* { dg-final { scan-assembler "\tvgather" } } */ +/* { dg-final { scan-assembler-not "addr32 vgather" } } */ + +typedef int __v8si __attribute__ ((__vector_size__ (32))); +typedef long long __m256i __attribute__ ((__vector_size__ (32), + __may_alias__)); +typedef unsigned char __mmask8; + +extern __inline void +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_prefetch_i32gather_pd (__m256i __index, void const *__addr, + int __scale, int __hint) +{ + __builtin_ia32_gatherpfdpd ((__mmask8) 0xFF, (__v8si) __index, __addr, + __scale, __hint); +} + +extern __inline void +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_mask_prefetch_i32gather_pd (__m256i __index, __mmask8 __mask, + void const *__addr, int __scale, int __hint) +{ + __builtin_ia32_gatherpfdpd (__mask, (__v8si) __index, __addr, __scale, + __hint); +} + +volatile __m256i idx; +volatile __mmask8 m8; +void *base; + +void extern +avx512pf_test (void) +{ + _mm512_prefetch_i32gather_pd (idx, base, 8, 3); + _mm512_mask_prefetch_i32gather_pd (idx, m8, base, 8, 3); +} diff --git a/gcc/testsuite/gcc.target/i386/pr89523-6.c b/gcc/testsuite/gcc.target/i386/pr89523-6.c new file mode 100644 index 00000000000..82f795e085c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr89523-6.c @@ -0,0 +1,38 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-require-effective-target maybe_x32 } */ +/* { dg-options "-mx32 -O2 -mavx512pf" } */ +/* { dg-final { scan-assembler-not "\tvgather" } } */ +/* { dg-final { scan-assembler "addr32 vgather" } } */ + +typedef int __v8si __attribute__ ((__vector_size__ (32))); +typedef long long __m256i __attribute__ ((__vector_size__ (32), + __may_alias__)); +typedef unsigned char __mmask8; + +extern __inline void +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_prefetch_i32gather_pd (__m256i __index, void const *__addr, + int __scale, int __hint) +{ + __builtin_ia32_gatherpfdpd ((__mmask8) 0xFF, (__v8si) __index, __addr, + __scale, __hint); +} + +extern __inline void +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_mask_prefetch_i32gather_pd (__m256i __index, __mmask8 __mask, + void const *__addr, int __scale, int __hint) +{ + __builtin_ia32_gatherpfdpd (__mask, (__v8si) __index, __addr, __scale, + __hint); +} + +volatile __m256i idx; +volatile __mmask8 m8; + +void extern +avx512pf_test (void) +{ + _mm512_prefetch_i32gather_pd (idx, (void *) 0, 8, 3); + _mm512_mask_prefetch_i32gather_pd (idx, m8, (void *) 0, 8, 3); +} diff --git a/gcc/testsuite/gcc.target/i386/pr89523-7.c b/gcc/testsuite/gcc.target/i386/pr89523-7.c new file mode 100644 index 00000000000..030b00d268a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr89523-7.c @@ -0,0 +1,42 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-require-effective-target maybe_x32 } */ +/* { dg-options "-mx32 -O2 -mavx512f" } */ +/* { dg-final { scan-assembler "\tvscatter" } } */ +/* { dg-final { scan-assembler-not "addr32 vscatter" } } */ + +typedef int __v8si __attribute__ ((__vector_size__ (32))); +typedef double __v8df __attribute__ ((__vector_size__ (64))); +typedef long long __m256i __attribute__ ((__vector_size__ (32), + __may_alias__)); +typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__)); +typedef unsigned char __mmask8; + +extern __inline void +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_i32scatter_pd (void *__addr, __m256i __index, __m512d __v1, + int __scale) +{ + __builtin_ia32_scattersiv8df (__addr, (__mmask8) 0xFF, + (__v8si) __index, (__v8df) __v1, __scale); +} + +extern __inline void +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_mask_i32scatter_pd (void *__addr, __mmask8 __mask, + __m256i __index, __m512d __v1, int __scale) +{ + __builtin_ia32_scattersiv8df (__addr, __mask, (__v8si) __index, + (__v8df) __v1, __scale); +} + +volatile __m512d src; +volatile __m256i idx; +volatile __mmask8 m8; +double *addr; + +void extern +avx512f_test (void) +{ + _mm512_i32scatter_pd (addr, idx, src, 8); + _mm512_mask_i32scatter_pd (addr, m8, idx, src, 8); +} diff --git a/gcc/testsuite/gcc.target/i386/pr89523-8.c b/gcc/testsuite/gcc.target/i386/pr89523-8.c new file mode 100644 index 00000000000..465c985c2b7 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr89523-8.c @@ -0,0 +1,41 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-require-effective-target maybe_x32 } */ +/* { dg-options "-mx32 -O2 -mavx512f" } */ +/* { dg-final { scan-assembler "\tvscatter" } } */ +/* { dg-final { scan-assembler-not "addr32 vscatter" } } */ + +typedef long long __v8di __attribute__ ((__vector_size__ (64))); +typedef double __v8df __attribute__ ((__vector_size__ (64))); +typedef long long __m512i __attribute__ ((__vector_size__ (64), __may_alias__)); +typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__)); +typedef unsigned char __mmask8; + +extern __inline void +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_i64scatter_pd (void *__addr, __m512i __index, __m512d __v1, + int __scale) +{ + __builtin_ia32_scatterdiv8df (__addr, (__mmask8) 0xFF, + (__v8di) __index, (__v8df) __v1, __scale); +} + +extern __inline void +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_mask_i64scatter_pd (void *__addr, __mmask8 __mask, + __m512i __index, __m512d __v1, int __scale) +{ + __builtin_ia32_scatterdiv8df (__addr, __mask, (__v8di) __index, + (__v8df) __v1, __scale); +} + +volatile __m512d src; +volatile __m512i idx; +volatile __mmask8 m8; +double *addr; + +void extern +avx512f_test (void) +{ + _mm512_i64scatter_pd (addr, idx, src, 8); + _mm512_mask_i64scatter_pd (addr, m8, idx, src, 8); +} diff --git a/gcc/testsuite/gcc.target/i386/pr89523-9.c b/gcc/testsuite/gcc.target/i386/pr89523-9.c new file mode 100644 index 00000000000..e9323126bd6 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr89523-9.c @@ -0,0 +1,30 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-require-effective-target maybe_x32 } */ +/* { dg-options "-mx32 -O2 -mavx512f" } */ +/* { dg-final { scan-assembler-not "\tvscatter" } } */ +/* { dg-final { scan-assembler "addr32 vscatter" } } */ + +typedef int __v8si __attribute__ ((__vector_size__ (32))); +typedef double __v8df __attribute__ ((__vector_size__ (64))); +typedef long long __m256i __attribute__ ((__vector_size__ (32), + __may_alias__)); +typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__)); +typedef unsigned char __mmask8; + +extern __inline void +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_i32scatter_pd (void *__addr, __m256i __index, __m512d __v1, + int __scale) +{ + __builtin_ia32_scattersiv8df (__addr, (__mmask8) 0xFF, + (__v8si) __index, (__v8df) __v1, __scale); +} + +volatile __m512d src; +volatile __m256i idx; + +void extern +avx512f_test (void) +{ + _mm512_i32scatter_pd ((void *) 0, idx, src, 8); +} -- 2.30.2