From fb06a28993e3e711db128bd806a8d765a7af2cd9 Mon Sep 17 00:00:00 2001 From: lkcl Date: Wed, 27 Jul 2022 13:38:50 +0100 Subject: [PATCH] --- nlnet_2022_opf_isa_wg.mdwn | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/nlnet_2022_opf_isa_wg.mdwn b/nlnet_2022_opf_isa_wg.mdwn index e6f2253e5..a6f916fda 100644 --- a/nlnet_2022_opf_isa_wg.mdwn +++ b/nlnet_2022_opf_isa_wg.mdwn @@ -44,7 +44,10 @@ as well as ongoing work on the Simulator. # Have you been involved with projects or organisations relevant to this project before? And if so, can you tell us a bit about your contributions? -A lot! +A lot! a full list is maintained here +and includes the world's first FOSSHW IEEE754 Formal Correctness Proofs for fadd, fsub, and fma; the world's first in-place Discrete Cosine Transform algorithm; +Significant improvements to Europe's only silicon-proven FOSSHW VLSI toolchain (coriolis2, by LIP6 Labs) to do an 800,000 transistor fully automated RTL2GDSII +tape-out; the side-benefits alone are enormous. # Requested Amount @@ -52,12 +55,6 @@ EUR 100,000. # Explain what the requested budget will be used for? -* Design and fabrication of Libre/Open Hardware Dual FPGA Carrier - boards (most likely accepting OrangeCrab as a module) -* Porting of both LibreBMC and OpenBMC to the FPGA Board -* Implementation of *server* side LPC (client-side already exists) -* Verilator simulation of both client and server side LPC - and testing of the two simulations back-to-back # Compare your own project with existing or historical efforts. -- 2.30.2