From fb434cfc91175bc80c39b3083ea3e5f96c835413 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 27 May 2020 17:12:03 +0100 Subject: [PATCH] LogicalOutputData does not need XER.so --- src/soc/fu/alu/output_stage.py | 5 ++++- src/soc/fu/logical/pipe_data.py | 6 ++---- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/src/soc/fu/alu/output_stage.py b/src/soc/fu/alu/output_stage.py index e228e871..1ee3a4a0 100644 --- a/src/soc/fu/alu/output_stage.py +++ b/src/soc/fu/alu/output_stage.py @@ -32,7 +32,10 @@ class ALUOutputStage(CommonOutputStage): # copy overflow and sticky-overflow comb += self.o.xer_so.data.eq(self.so) - comb += self.o.xer_so.ok.eq(op.oe.oe & op.oe.oe_ok) # SO is to be set + # SO is to be set - however to save regfile port requests, only set + # if the data actually changes. only possible due to pass-thru + with m.If(self.i.xer_so.data != self.so): + comb += self.o.xer_so.ok.eq(op.oe.oe & op.oe.oe_ok) comb += self.o.xer_ov.data.eq(ov) comb += self.o.xer_ov.ok.eq(op.oe.oe & op.oe.oe_ok) # OV/32 is to be set diff --git a/src/soc/fu/logical/pipe_data.py b/src/soc/fu/logical/pipe_data.py index 35d637ae..ccb6d95e 100644 --- a/src/soc/fu/logical/pipe_data.py +++ b/src/soc/fu/logical/pipe_data.py @@ -30,27 +30,25 @@ class LogicalOutputData(IntegerData): regspec = [('INT', 'o', '0:63'), ('CR', 'cr0', '0:3'), ('XER', 'xer_ca', '34,45'), - ('XER', 'xer_so', '32')] + ] def __init__(self, pspec): super().__init__(pspec) self.o = Data(64, name="stage_o") # RT self.cr0 = Data(4, name="cr0") self.xer_ca = Data(2, name="xer_co") # bit0: ca, bit1: ca32 - self.xer_so = Data(1, name="xer_so") def __iter__(self): yield from super().__iter__() yield self.o yield self.xer_ca yield self.cr0 - yield self.xer_so def eq(self, i): lst = super().eq(i) return lst + [self.o.eq(i.o), self.xer_ca.eq(i.xer_ca), self.cr0.eq(i.cr0), - self.xer_so.eq(i.xer_so)] + ] class LogicalPipeSpec(CommonPipeSpec): -- 2.30.2