From fb5397aa82b50e0e6e9c0716e50a01e26e2c740b Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sat, 9 May 2015 15:48:54 +0200 Subject: [PATCH] uart: remove litescope dependency for UARTWishboneBridge and remove frontend --- misoclib/com/liteeth/example_designs/targets/base.py | 2 +- misoclib/com/litepcie/example_designs/targets/dma.py | 2 +- misoclib/com/liteusb/frontend/wishbone.py | 6 +++--- misoclib/com/uart/frontend/__init__.py | 0 misoclib/com/uart/{frontend => }/wishbone.py | 6 +++--- misoclib/mem/litesata/example_designs/targets/bist.py | 2 +- .../tools/litescope/example_designs/targets/simple.py | 2 +- misoclib/tools/{litescope/frontend => }/wishbone.py | 8 ++++---- 8 files changed, 14 insertions(+), 14 deletions(-) delete mode 100644 misoclib/com/uart/frontend/__init__.py rename misoclib/com/uart/{frontend => }/wishbone.py (52%) rename misoclib/tools/{litescope/frontend => }/wishbone.py (96%) diff --git a/misoclib/com/liteeth/example_designs/targets/base.py b/misoclib/com/liteeth/example_designs/targets/base.py index 582e50bc..99b117c8 100644 --- a/misoclib/com/liteeth/example_designs/targets/base.py +++ b/misoclib/com/liteeth/example_designs/targets/base.py @@ -7,7 +7,7 @@ from misoclib.tools.litescope.common import * from misoclib.tools.litescope.frontend.la import LiteScopeLA from misoclib.tools.litescope.core.port import LiteScopeTerm -from misoclib.com.uart.frontend.wishbone import UARTWishboneBridge +from misoclib.com.uart.wishbone import UARTWishboneBridge from misoclib.com.liteeth.common import * from misoclib.com.liteeth.phy.gmii import LiteEthPHYGMII diff --git a/misoclib/com/litepcie/example_designs/targets/dma.py b/misoclib/com/litepcie/example_designs/targets/dma.py index f1291355..c4c9e550 100644 --- a/misoclib/com/litepcie/example_designs/targets/dma.py +++ b/misoclib/com/litepcie/example_designs/targets/dma.py @@ -7,7 +7,7 @@ from migen.genlib.misc import timeline from misoclib.soc import SoC from misoclib.tools.litescope.common import * -from misoclib.com.uart.frontend.wishbone import UARTWishboneBridge +from misoclib.com.uart.wishbone import UARTWishboneBridge from misoclib.com.litepcie.phy.s7pciephy import S7PCIEPHY from misoclib.com.litepcie.core import Endpoint diff --git a/misoclib/com/liteusb/frontend/wishbone.py b/misoclib/com/liteusb/frontend/wishbone.py index c2c00d30..394e2c4c 100644 --- a/misoclib/com/liteusb/frontend/wishbone.py +++ b/misoclib/com/liteusb/frontend/wishbone.py @@ -1,9 +1,9 @@ from migen.fhdl.std import * from misoclib.com.liteusb.common import * -from misoclib.tools.litescope.frontend.wishbone import LiteScopeWishboneBridge +from misoclib.tools.wishbone import WishboneStreamingBridge -class LiteUSBWishboneBridge(LiteScopeWishboneBridge): +class LiteUSBWishboneBridge(WishboneStreamingBridge): def __init__(self, port, clk_freq): - LiteScopeWishboneBridge.__init__(self, port, clk_freq) + WishboneStreamingBridge.__init__(self, port, clk_freq) self.comb += port.sink.dst.eq(port.tag) diff --git a/misoclib/com/uart/frontend/__init__.py b/misoclib/com/uart/frontend/__init__.py deleted file mode 100644 index e69de29b..00000000 diff --git a/misoclib/com/uart/frontend/wishbone.py b/misoclib/com/uart/wishbone.py similarity index 52% rename from misoclib/com/uart/frontend/wishbone.py rename to misoclib/com/uart/wishbone.py index d1499865..fc0d292e 100644 --- a/misoclib/com/uart/frontend/wishbone.py +++ b/misoclib/com/uart/wishbone.py @@ -1,9 +1,9 @@ from migen.fhdl.std import * -from misoclib.tools.litescope.frontend.wishbone import LiteScopeWishboneBridge +from misoclib.tools.wishbone import WishboneStreamingBridge from misoclib.com.uart.phy.serial import UARTPHYSerial -class UARTWishboneBridge(LiteScopeWishboneBridge): +class UARTWishboneBridge(WishboneStreamingBridge): def __init__(self, pads, clk_freq, baudrate=115200): self.submodules.phy = UARTPHYSerial(pads, clk_freq, baudrate) - LiteScopeWishboneBridge.__init__(self, self.phy, clk_freq) + WishboneStreamingBridge.__init__(self, self.phy, clk_freq) diff --git a/misoclib/mem/litesata/example_designs/targets/bist.py b/misoclib/mem/litesata/example_designs/targets/bist.py index 8b28dfe3..ce7d53a1 100644 --- a/misoclib/mem/litesata/example_designs/targets/bist.py +++ b/misoclib/mem/litesata/example_designs/targets/bist.py @@ -9,7 +9,7 @@ from misoclib.tools.litescope.common import * from misoclib.tools.litescope.frontend.la import LiteScopeLA from misoclib.tools.litescope.core.port import LiteScopeTerm -from misoclib.com.uart.frontend.wishbone import UARTWishboneBridge +from misoclib.com.uart.wishbone import UARTWishboneBridge from misoclib.mem.litesata.common import * from misoclib.mem.litesata.phy import LiteSATAPHY diff --git a/misoclib/tools/litescope/example_designs/targets/simple.py b/misoclib/tools/litescope/example_designs/targets/simple.py index efbe3397..26853f7e 100644 --- a/misoclib/tools/litescope/example_designs/targets/simple.py +++ b/misoclib/tools/litescope/example_designs/targets/simple.py @@ -7,7 +7,7 @@ from misoclib.tools.litescope.core.port import LiteScopeTerm from misoclib.tools.litescope.frontend.io import LiteScopeIO from misoclib.tools.litescope.frontend.la import LiteScopeLA -from misoclib.com.uart.frontend.wishbone import UARTWishboneBridge +from misoclib.com.uart.wishbone import UARTWishboneBridge class LiteScopeSoC(SoC, AutoCSR): csr_map = { diff --git a/misoclib/tools/litescope/frontend/wishbone.py b/misoclib/tools/wishbone.py similarity index 96% rename from misoclib/tools/litescope/frontend/wishbone.py rename to misoclib/tools/wishbone.py index e7e00660..50ab287f 100644 --- a/misoclib/tools/litescope/frontend/wishbone.py +++ b/misoclib/tools/wishbone.py @@ -1,12 +1,12 @@ -from misoclib.tools.litescope.common import * +from migen.fhdl.std import * from migen.bus import wishbone -from migen.genlib.misc import chooser +from migen.genlib.misc import chooser, Counter, Timeout from migen.genlib.record import Record +from migen.genlib.fsm import FSM, NextState from migen.flow.actor import Sink, Source -from misoclib.com.uart.phy.serial import UARTPHYSerial -class LiteScopeWishboneBridge(Module): +class WishboneStreamingBridge(Module): cmds = { "write": 0x01, "read": 0x02 -- 2.30.2