From fb55ee17219ac510f580d5a41e4e54bac7de61cb Mon Sep 17 00:00:00 2001 From: whitequark Date: Thu, 13 Dec 2018 03:51:00 +0000 Subject: [PATCH] back.rtlil: explain logic for CD reset insertion. --- nmigen/back/rtlil.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/nmigen/back/rtlil.py b/nmigen/back/rtlil.py index 9ef5a23..490e3e7 100644 --- a/nmigen/back/rtlil.py +++ b/nmigen/back/rtlil.py @@ -510,6 +510,8 @@ def convert_fragment(builder, fragment, name, top, clock_domains): def convert(fragment, ports=[], clock_domains={}): + # Clock domain reset always takes priority over all other logic. To ensure this, insert + # decision trees for clock domain reset as the very last step before synthesis. fragment = xfrm.ResetInserter({ cd.name: cd.reset for cd in clock_domains.values() if cd.reset is not None })(fragment) -- 2.30.2