From fb58a927888305a929cbff4dcae2234ede55bb60 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 1 May 2021 20:31:08 +0100 Subject: [PATCH] store data in microwatt dcache goes in one cycle AFTER valid is set --- src/soc/fu/mmu/fsm.py | 15 ++++++++++++--- src/soc/simple/test/test_issuer_mmu.py | 8 ++++---- 2 files changed, 16 insertions(+), 7 deletions(-) diff --git a/src/soc/fu/mmu/fsm.py b/src/soc/fu/mmu/fsm.py index a31b8100..d7d52f37 100644 --- a/src/soc/fu/mmu/fsm.py +++ b/src/soc/fu/mmu/fsm.py @@ -47,11 +47,16 @@ class LoadStore1(PortInterfaceBase): # TODO, convert dcache wb_in/wb_out to "standard" nmigen Wishbone bus self.dbus = Record(make_wb_layout(pspec)) + # for creating a single clock blip to DCache + self.d_valid = Signal() + self.d_validblip = Signal() + def set_wr_addr(self, m, addr, mask): #m.d.comb += self.l_in.valid.eq(1) #m.d.comb += self.l_in.addr.eq(addr) #m.d.comb += self.l_in.load.eq(0) - m.d.comb += self.d_in.valid.eq(1) + m.d.comb += self.d_valid.eq(1) + m.d.comb += self.d_in.valid.eq(self.d_validblip) m.d.comb += self.d_in.load.eq(0) m.d.comb += self.d_in.byte_sel.eq(mask) # set phys addr on both units @@ -63,7 +68,8 @@ class LoadStore1(PortInterfaceBase): #m.d.comb += self.l_in.valid.eq(1) #m.d.comb += self.l_in.load.eq(1) #m.d.comb += self.l_in.addr.eq(addr) - m.d.comb += self.d_in.valid.eq(1) + m.d.comb += self.d_valid.eq(1) + m.d.comb += self.d_in.valid.eq(self.d_validblip) m.d.comb += self.d_in.load.eq(1) m.d.comb += self.d_in.byte_sel.eq(mask) m.d.comb += self.d_in.addr.eq(addr) @@ -72,7 +78,7 @@ class LoadStore1(PortInterfaceBase): return None #FIXME return value def set_wr_data(self, m, data, wen): - m.d.comb += self.d_in.data.eq(data) + m.d.sync += self.d_in.data.eq(data) # one cycle **AFTER** valid raised # TODO set wen st_ok = Const(1, 1) return st_ok @@ -160,6 +166,9 @@ class LoadStore1(PortInterfaceBase): if hasattr(dbus, "stall"): comb += dcache.wb_in.stall.eq(dbus.stall) + # create a blip (single pulse) on valid read/write request + m.d.comb += self.d_validblip.eq(rising_edge(m, self.d_valid)) + return m def ports(self): diff --git a/src/soc/simple/test/test_issuer_mmu.py b/src/soc/simple/test/test_issuer_mmu.py index bafcf3b1..f35dbe15 100644 --- a/src/soc/simple/test/test_issuer_mmu.py +++ b/src/soc/simple/test/test_issuer_mmu.py @@ -37,12 +37,12 @@ if __name__ == "__main__": suite = unittest.TestSuite() #suite.addTest(TestRunner(GeneralTestCases.test_data, svp64=svp64, # microwatt_mmu=True)) - suite.addTest(TestRunner(MMUTestCase().test_data, svp64=svp64, - microwatt_mmu=True)) + #suite.addTest(TestRunner(MMUTestCase().test_data, svp64=svp64, + # microwatt_mmu=True)) # without ROM set - suite.addTest(TestRunner(MMUTestCaseROM().test_data, svp64=svp64, - microwatt_mmu=True)) + #suite.addTest(TestRunner(MMUTestCaseROM().test_data, svp64=svp64, + # microwatt_mmu=True)) # LD/ST tests should all still work suite.addTest(TestRunner(LDSTTestCase().test_data, svp64=svp64, -- 2.30.2