From fb728653b626594d13ae0fbf78e33c108cf8a8da Mon Sep 17 00:00:00 2001 From: Segher Boessenkool Date: Thu, 9 Apr 2015 16:37:14 +0200 Subject: [PATCH] re PR rtl-optimization/65693 (ICE in assign_by_spills, at lra-assigns.c:1419) PR rtl-optimization/65693 * combine.c (is_parallel_of_n_reg_sets): Move outside of #ifndef HAVE_cc0. From-SVN: r221951 --- gcc/ChangeLog | 6 ++++++ gcc/combine.c | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 36e027add25..4d1a189fdaa 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2015-04-09 Segher Boessenkool + + PR rtl-optimization/65693 + * combine.c (is_parallel_of_n_reg_sets): Move outside of + #ifndef HAVE_cc0. + 2015-04-09 Georg-Johann Lay PR target/65296 diff --git a/gcc/combine.c b/gcc/combine.c index 6f4a8da9761..46cd6db62ad 100644 --- a/gcc/combine.c +++ b/gcc/combine.c @@ -2492,7 +2492,6 @@ update_cfg_for_uncondjump (rtx_insn *insn) } } -#ifndef HAVE_cc0 /* Return whether PAT is a PARALLEL of exactly N register SETs followed by an arbitrary number of CLOBBERs. */ static bool @@ -2517,6 +2516,7 @@ is_parallel_of_n_reg_sets (rtx pat, int n) return true; } +#ifndef HAVE_cc0 /* Return whether INSN, a PARALLEL of N register SETs (and maybe some CLOBBERs), can be split into individual SETs in that order, without changing semantics. */ -- 2.30.2