From fb9e6a4bf8fb2a6aee9fd5c2dd0d0f4c842cf9f1 Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Thu, 29 Nov 2018 23:15:42 +0100 Subject: [PATCH] re PR target/54700 (Optimize away x<0 as mask argument of a blend.) PR target/54700 * config/i386/sse.md (*_blendv_lt, *_blendv_ltint, *_pblendvb_lt): Change define_insn into define_insn_and_split. From-SVN: r266648 --- gcc/ChangeLog | 9 +++++++++ gcc/config/i386/sse.md | 41 ++++++++++++++++++++++++++--------------- 2 files changed, 35 insertions(+), 15 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 0985331bc65..93ee3fad3e7 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,12 @@ +2018-11-29 Jakub Jelinek + + PR target/54700 + * config/i386/sse.md + (*_blendv_lt, + *_blendv_ltint, + *_pblendvb_lt): Change define_insn into + define_insn_and_split. + 2018-11-29 Peter Bergner PR target/87496 diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 3f3b1c97ad5..b4d355e40b2 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -15682,7 +15682,7 @@ ] (const_string "")))]) -(define_insn "*_blendv_lt" +(define_insn_and_split "*_blendv_lt" [(set (match_operand:VF_128_256 0 "register_operand" "=Yr,*x,x") (unspec:VF_128_256 [(match_operand:VF_128_256 1 "register_operand" "0,0,x") @@ -15693,10 +15693,12 @@ (match_operand: 4 "const0_operand" "C,C,C")) 0)] UNSPEC_BLENDV))] "TARGET_SSE4_1" - "@ - blendv\t{%3, %2, %0|%0, %2, %3} - blendv\t{%3, %2, %0|%0, %2, %3} - vblendv\t{%3, %2, %1, %0|%0, %1, %2, %3}" + "#" + "&& reload_completed" + [(set (match_dup 0) + (unspec:VF_128_256 + [(match_dup 1) (match_dup 2) (match_dup 3)] UNSPEC_BLENDV))] + "operands[3] = gen_lowpart (mode, operands[3]);" [(set_attr "isa" "noavx,noavx,avx") (set_attr "type" "ssemov") (set_attr "length_immediate" "1") @@ -15712,7 +15714,7 @@ (define_mode_attr ssefltvecmode [(V2DI "V2DF") (V4DI "V4DF") (V4SI "V4SF") (V8SI "V8SF")]) -(define_insn "*_blendv_ltint" +(define_insn_and_split "*_blendv_ltint" [(set (match_operand: 0 "register_operand" "=Yr,*x,x") (unspec: [(match_operand: 1 "register_operand" "0,0,x") @@ -15723,10 +15725,17 @@ (match_operand:VI48_AVX 4 "const0_operand" "C,C,C")) 0)] UNSPEC_BLENDV))] "TARGET_SSE4_1" - "@ - blendv\t{%3, %2, %0|%0, %2, %3} - blendv\t{%3, %2, %0|%0, %2, %3} - vblendv\t{%3, %2, %1, %0|%0, %1, %2, %3}" + "#" + "&& reload_completed" + [(set (match_dup 0) + (unspec: + [(match_dup 1) (match_dup 2) (match_dup 3)] UNSPEC_BLENDV))] +{ + operands[0] = gen_lowpart (mode, operands[0]); + operands[1] = gen_lowpart (mode, operands[1]); + operands[2] = gen_lowpart (mode, operands[2]); + operands[3] = gen_lowpart (mode, operands[3]); +} [(set_attr "isa" "noavx,noavx,avx") (set_attr "type" "ssemov") (set_attr "length_immediate" "1") @@ -15834,7 +15843,7 @@ (set_attr "btver2_decode" "vector,vector,vector") (set_attr "mode" "")]) -(define_insn "*_pblendvb_lt" +(define_insn_and_split "*_pblendvb_lt" [(set (match_operand:VI1_AVX2 0 "register_operand" "=Yr,*x,x") (unspec:VI1_AVX2 [(match_operand:VI1_AVX2 1 "register_operand" "0,0,x") @@ -15843,10 +15852,12 @@ (match_operand:VI1_AVX2 4 "const0_operand" "C,C,C"))] UNSPEC_BLENDV))] "TARGET_SSE4_1" - "@ - pblendvb\t{%3, %2, %0|%0, %2, %3} - pblendvb\t{%3, %2, %0|%0, %2, %3} - vpblendvb\t{%3, %2, %1, %0|%0, %1, %2, %3}" + "#" + "" + [(set (match_dup 0) + (unspec:VI1_AVX2 + [(match_dup 1) (match_dup 2) (match_dup 3)] UNSPEC_BLENDV))] + "" [(set_attr "isa" "noavx,noavx,avx") (set_attr "type" "ssemov") (set_attr "prefix_extra" "1") -- 2.30.2