From fbb65119f40b7c1c10c05e7fa023972f924fa99e Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Wed, 6 Apr 2022 21:21:03 -0700 Subject: [PATCH] remove unused imports --- src/nmigen_gf/hdl/cldivrem.py | 2 +- src/nmigen_gf/hdl/test/test_cldivrem.py | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/nmigen_gf/hdl/cldivrem.py b/src/nmigen_gf/hdl/cldivrem.py index ae631c8..4ce94ce 100644 --- a/src/nmigen_gf/hdl/cldivrem.py +++ b/src/nmigen_gf/hdl/cldivrem.py @@ -10,7 +10,7 @@ https://bugs.libre-soc.org/show_bug.cgi?id=784 """ from nmigen.hdl.ir import Elaboratable -from nmigen.hdl.ast import Signal, Cat +from nmigen.hdl.ast import Signal from nmigen.hdl.dsl import Module diff --git a/src/nmigen_gf/hdl/test/test_cldivrem.py b/src/nmigen_gf/hdl/test/test_cldivrem.py index 5929f67..b6e4cfb 100644 --- a/src/nmigen_gf/hdl/test/test_cldivrem.py +++ b/src/nmigen_gf/hdl/test/test_cldivrem.py @@ -5,7 +5,7 @@ # of Horizon 2020 EU Programme 957073. import unittest -from nmigen.hdl.ast import (AnyConst, Assert, Signal, Const, unsigned, Cat) +from nmigen.hdl.ast import AnyConst, Assert, Signal, Const, unsigned from nmigen.hdl.dsl import Module from nmutil.formaltest import FHDLTestCase from nmigen_gf.hdl.cldivrem import (equal_leading_zero_count_reference, -- 2.30.2