From fbbe3d4b75be9e6ac834feda5f5ce12af088b6be Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Mon, 27 Apr 2020 16:04:05 -0400 Subject: [PATCH] pan/bi: Use common IR indices Signed-off-by: Alyssa Rosenzweig Part-of: --- src/panfrost/bifrost/bi_lower_combine.c | 2 +- src/panfrost/bifrost/bi_print.c | 2 +- src/panfrost/bifrost/bi_special.c | 12 ++++---- src/panfrost/bifrost/bifrost_compile.c | 24 ++++++++-------- src/panfrost/bifrost/compiler.h | 37 ++----------------------- src/panfrost/util/pan_ir.h | 4 +-- 6 files changed, 24 insertions(+), 57 deletions(-) diff --git a/src/panfrost/bifrost/bi_lower_combine.c b/src/panfrost/bifrost/bi_lower_combine.c index 8cbe42c54d0..f915e3df227 100644 --- a/src/panfrost/bifrost/bi_lower_combine.c +++ b/src/panfrost/bifrost/bi_lower_combine.c @@ -167,7 +167,7 @@ bi_lower_combine_src(bi_context *ctx, bi_instruction *ins, unsigned s, unsigned /* We currently only handle SSA */ if (!src) return false; - if (src & (BIR_SPECIAL | BIR_IS_REG)) return false; + if (src & (BIR_SPECIAL | PAN_IS_REG)) return false; /* We are SSA. Lookup the generating instruction. */ unsigned bytes = nir_alu_type_get_type_size(ins->dest_type) / 8; diff --git a/src/panfrost/bifrost/bi_print.c b/src/panfrost/bifrost/bi_print.c index 1c9c8a72a31..e9e737d662a 100644 --- a/src/panfrost/bifrost/bi_print.c +++ b/src/panfrost/bifrost/bi_print.c @@ -166,7 +166,7 @@ bi_print_dest_index(FILE *fp, bi_instruction *ins, unsigned index) fprintf(fp, "_"); else if (index & BIR_INDEX_REGISTER) fprintf(fp, "br%u", index & ~BIR_INDEX_REGISTER); - else if (index & BIR_IS_REG) + else if (index & PAN_IS_REG) fprintf(fp, "r%u", index >> 1); else if (!(index & BIR_SPECIAL)) fprintf(fp, "%u", (index >> 1) - 1); diff --git a/src/panfrost/bifrost/bi_special.c b/src/panfrost/bifrost/bi_special.c index d3d78a9acf6..4cb9e151631 100644 --- a/src/panfrost/bifrost/bi_special.c +++ b/src/panfrost/bifrost/bi_special.c @@ -43,7 +43,7 @@ bi_emit_fexp2_new(bi_context *ctx, nir_alu_instr *instr) .dest = bi_make_temp(ctx), .dest_type = nir_type_float32, .src = { - bir_src_index(&instr->src[0].src), + pan_src_index(&instr->src[0].src), BIR_INDEX_CONSTANT | 0, BIR_INDEX_ZERO, BIR_INDEX_CONSTANT | 32, @@ -77,7 +77,7 @@ bi_emit_fexp2_new(bi_context *ctx, nir_alu_instr *instr) bi_instruction fexp = { .type = BI_SPECIAL, .op = { .special = BI_SPECIAL_EXP2_LOW }, - .dest = bir_dest_index(&instr->dest.dest), + .dest = pan_dest_index(&instr->dest.dest), .dest_type = nir_type_float32, .src = { f2i.dest, mscale.src[0] }, .src_types = { nir_type_int32, nir_type_float32 }, @@ -99,7 +99,7 @@ bi_emit_flog2_new(bi_context *ctx, nir_alu_instr *instr) .op = { .frexp = BI_FREXPE_LOG }, .dest = bi_make_temp(ctx), .dest_type = nir_type_int32, - .src = { bir_src_index(&instr->src[0].src) }, + .src = { pan_src_index(&instr->src[0].src) }, .src_types = { nir_type_float32 } }; @@ -121,7 +121,7 @@ bi_emit_flog2_new(bi_context *ctx, nir_alu_instr *instr) .dest_type = nir_type_float32, .src = { BIR_INDEX_CONSTANT, - bir_src_index(&instr->src[0].src), + pan_src_index(&instr->src[0].src), }, .src_types = { nir_type_float32, nir_type_float32 }, .constant = { @@ -135,14 +135,14 @@ bi_emit_flog2_new(bi_context *ctx, nir_alu_instr *instr) .op = { .table = BI_TABLE_LOG2_U_OVER_U_1_LOW }, .dest = bi_make_temp(ctx), .dest_type = nir_type_float32, - .src = { bir_src_index(&instr->src[0].src) }, + .src = { pan_src_index(&instr->src[0].src) }, .src_types = { nir_type_float32 }, }; /* FMA log2(x)/(x - 1), (x - 1), M */ bi_instruction fma = { .type = BI_FMA, - .dest = bir_dest_index(&instr->dest.dest), + .dest = pan_dest_index(&instr->dest.dest), .dest_type = nir_type_float32, .src = { help.dest, diff --git a/src/panfrost/bifrost/bifrost_compile.c b/src/panfrost/bifrost/bifrost_compile.c index ad3cdd90449..1586bdcbe2c 100644 --- a/src/panfrost/bifrost/bifrost_compile.c +++ b/src/panfrost/bifrost/bifrost_compile.c @@ -73,7 +73,7 @@ bi_load(enum bi_class T, nir_intrinsic_instr *instr) const nir_intrinsic_info *info = &nir_intrinsic_infos[instr->intrinsic]; if (info->has_dest) - load.dest = bir_dest_index(&instr->dest); + load.dest = pan_dest_index(&instr->dest); if (info->has_dest && info->index_map[NIR_INTRINSIC_TYPE] > 0) load.dest_type = nir_intrinsic_type(instr); @@ -83,7 +83,7 @@ bi_load(enum bi_class T, nir_intrinsic_instr *instr) if (nir_src_is_const(*offset)) load.constant.u64 += nir_src_as_uint(*offset); else - load.src[0] = bir_src_index(offset); + load.src[0] = pan_src_index(offset); return load; } @@ -116,7 +116,7 @@ bi_emit_frag_out(bi_context *ctx, nir_intrinsic_instr *instr) .type = BI_ATEST, .src = { BIR_INDEX_REGISTER | 60 /* TODO: RA */, - bir_src_index(&instr->src[0]) + pan_src_index(&instr->src[0]) }, .src_types = { nir_type_uint32, @@ -139,7 +139,7 @@ bi_emit_frag_out(bi_context *ctx, nir_intrinsic_instr *instr) .type = BI_BLEND, .blend_location = nir_intrinsic_base(instr), .src = { - bir_src_index(&instr->src[0]), + pan_src_index(&instr->src[0]), BIR_INDEX_REGISTER | 60 /* Can this be arbitrary? */, }, .src_types = { @@ -190,7 +190,7 @@ bi_emit_st_vary(bi_context *ctx, nir_intrinsic_instr *instr) bi_instruction st = { .type = BI_STORE_VAR, .src = { - bir_src_index(&instr->src[0]), + pan_src_index(&instr->src[0]), address.dest, address.dest, address.dest, }, .src_types = { @@ -249,7 +249,7 @@ bi_emit_sysval(bi_context *ctx, nir_instr *instr, .src = { BIR_INDEX_CONSTANT, BIR_INDEX_ZERO }, .src_types = { nir_type_uint32, nir_type_uint32 }, .constant = { (uniform * 16) + offset }, - .dest = bir_dest_index(&nir_dest), + .dest = pan_dest_index(&nir_dest), .dest_type = nir_type_uint32, /* TODO */ }; @@ -317,7 +317,7 @@ emit_load_const(bi_context *ctx, nir_load_const_instr *instr) bi_instruction move = { .type = BI_MOV, - .dest = bir_ssa_index(&instr->def), + .dest = pan_ssa_index(&instr->def), .dest_type = instr->def.bit_size | nir_type_uint, .src = { BIR_INDEX_CONSTANT @@ -500,7 +500,7 @@ bi_copy_src(bi_instruction *alu, nir_alu_instr *instr, unsigned i, unsigned to, return; } - alu->src[to] = bir_src_index(&instr->src[i].src); + alu->src[to] = pan_src_index(&instr->src[i].src); /* Copy swizzle for all vectored components, replicating last component * to fill undersized */ @@ -561,7 +561,7 @@ emit_alu(bi_context *ctx, nir_alu_instr *instr) /* Otherwise, assume it's something we can handle normally */ bi_instruction alu = { .type = bi_class_for_nir_alu(instr->op), - .dest = bir_dest_index(&instr->dest.dest), + .dest = pan_dest_index(&instr->dest.dest), .dest_type = nir_op_infos[instr->op].output_type | nir_dest_bit_size(instr->dest.dest), }; @@ -698,14 +698,14 @@ emit_tex_compact(bi_context *ctx, nir_tex_instr *instr) bi_instruction tex = { .type = BI_TEX, .op = { .texture = BI_TEX_COMPACT }, - .dest = bir_dest_index(&instr->dest), + .dest = pan_dest_index(&instr->dest), .dest_type = instr->dest_type, .src_types = { nir_type_float32, nir_type_float32 }, .vector_channels = 4 }; for (unsigned i = 0; i < instr->num_srcs; ++i) { - int index = bir_src_index(&instr->src[i].src); + int index = pan_src_index(&instr->src[i].src); assert (instr->src[i].src_type == nir_tex_src_coord); tex.src[0] = index; @@ -853,7 +853,7 @@ static void bi_set_branch_cond(bi_instruction *branch, nir_src *cond, bool invert) { /* TODO: Try to unwrap instead of always bailing */ - branch->src[0] = bir_src_index(cond); + branch->src[0] = pan_src_index(cond); branch->src[1] = BIR_INDEX_ZERO; branch->src_types[0] = branch->src_types[1] = nir_type_uint16; branch->branch.cond = invert ? BI_COND_EQ : BI_COND_NE; diff --git a/src/panfrost/bifrost/compiler.h b/src/panfrost/bifrost/compiler.h index 0716cf342ef..97761643966 100644 --- a/src/panfrost/bifrost/compiler.h +++ b/src/panfrost/bifrost/compiler.h @@ -223,7 +223,7 @@ typedef struct { struct list_head link; /* Must be first */ enum bi_class type; - /* Indices, see bir_ssa_index etc. Note zero is special cased + /* Indices, see pan_ssa_index etc. Note zero is special cased * to "no argument" */ unsigned dest; unsigned src[BIR_SRC_COUNT]; @@ -419,10 +419,6 @@ bi_remove_instruction(bi_instruction *ins) list_del(&ins->link); } -/* So we can distinguish between SSA/reg/sentinel quickly */ -#define BIR_NO_ARG (0) -#define BIR_IS_REG (1) - /* If high bits are set, instead of SSA/registers, we have specials indexed by * the low bits if necessary. * @@ -460,36 +456,7 @@ bi_make_temp(bi_context *ctx) static inline unsigned bi_make_temp_reg(bi_context *ctx) { - return ((ctx->impl->reg_alloc + ctx->temp_alloc++) << 1) | BIR_IS_REG; -} - -static inline unsigned -bir_ssa_index(nir_ssa_def *ssa) -{ - /* Off-by-one ensures BIR_NO_ARG is skipped */ - return ((ssa->index + 1) << 1) | 0; -} - -static inline unsigned -bir_src_index(nir_src *src) -{ - if (src->is_ssa) - return bir_ssa_index(src->ssa); - else { - assert(!src->reg.indirect); - return (src->reg.reg->index << 1) | BIR_IS_REG; - } -} - -static inline unsigned -bir_dest_index(nir_dest *dst) -{ - if (dst->is_ssa) - return bir_ssa_index(&dst->ssa); - else { - assert(!dst->reg.indirect); - return (dst->reg.reg->index << 1) | BIR_IS_REG; - } + return ((ctx->impl->reg_alloc + ctx->temp_alloc++) << 1) | PAN_IS_REG; } /* Iterators for Bifrost IR */ diff --git a/src/panfrost/util/pan_ir.h b/src/panfrost/util/pan_ir.h index 7eb51fa5df1..5b00edae5f2 100644 --- a/src/panfrost/util/pan_ir.h +++ b/src/panfrost/util/pan_ir.h @@ -195,7 +195,7 @@ pan_src_index(nir_src *src) return pan_ssa_index(src->ssa); else { assert(!src->reg.indirect); - return (src->reg.reg->index << 1) | BIR_IS_REG; + return (src->reg.reg->index << 1) | PAN_IS_REG; } } @@ -206,7 +206,7 @@ pan_dest_index(nir_dest *dst) return pan_ssa_index(&dst->ssa); else { assert(!dst->reg.indirect); - return (dst->reg.reg->index << 1) | BIR_IS_REG; + return (dst->reg.reg->index << 1) | PAN_IS_REG; } } -- 2.30.2