From fbc932e72cff3eb14122acb92415bbc0def82d74 Mon Sep 17 00:00:00 2001 From: Edmar Wienskoski Date: Mon, 4 Jun 2012 18:44:53 +0000 Subject: [PATCH] re PR target/53559 (ICE on altivec builtins stv[l|r]x[l]) 2012-06-04 Edmar Wienskoski PR target/53559 * config/rs6000/altivec.md (altivec_stvlx): Change machine mode of operands. (altivec_stvlxl): Ditto. (altivec_stvrx): Ditto. (altivec_stvrxl): Ditto. gcc/testsuite 2012-06-04 Edmar Wienskoski PR target/53559 * gcc.target/powerpc/cell_builtin_1.c: New test case. * gcc.target/powerpc/cell_builtin_2.c: Ditto. * gcc.target/powerpc/cell_builtin_3.c: Ditto. * gcc.target/powerpc/cell_builtin_4.c: Ditto. * gcc.target/powerpc/cell_builtin_5.c: Ditto. * gcc.target/powerpc/cell_builtin_6.c: Ditto. * gcc.target/powerpc/cell_builtin_7.c: Ditto. * gcc.target/powerpc/cell_builtin_8.c: Ditto. From-SVN: r188200 --- gcc/ChangeLog | 9 ++++ gcc/config/rs6000/altivec.md | 16 +++---- gcc/testsuite/ChangeLog | 12 +++++ .../gcc.target/powerpc/cell_builtin-1.c | 48 +++++++++++++++++++ .../gcc.target/powerpc/cell_builtin-2.c | 48 +++++++++++++++++++ .../gcc.target/powerpc/cell_builtin-3.c | 48 +++++++++++++++++++ .../gcc.target/powerpc/cell_builtin-4.c | 48 +++++++++++++++++++ .../gcc.target/powerpc/cell_builtin-5.c | 48 +++++++++++++++++++ .../gcc.target/powerpc/cell_builtin-6.c | 48 +++++++++++++++++++ .../gcc.target/powerpc/cell_builtin-7.c | 48 +++++++++++++++++++ .../gcc.target/powerpc/cell_builtin-8.c | 48 +++++++++++++++++++ 11 files changed, 413 insertions(+), 8 deletions(-) create mode 100644 gcc/testsuite/gcc.target/powerpc/cell_builtin-1.c create mode 100644 gcc/testsuite/gcc.target/powerpc/cell_builtin-2.c create mode 100644 gcc/testsuite/gcc.target/powerpc/cell_builtin-3.c create mode 100644 gcc/testsuite/gcc.target/powerpc/cell_builtin-4.c create mode 100644 gcc/testsuite/gcc.target/powerpc/cell_builtin-5.c create mode 100644 gcc/testsuite/gcc.target/powerpc/cell_builtin-6.c create mode 100644 gcc/testsuite/gcc.target/powerpc/cell_builtin-7.c create mode 100644 gcc/testsuite/gcc.target/powerpc/cell_builtin-8.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 9151e7d4ab4..2cf78684a92 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,12 @@ +2012-06-04 Edmar Wienskoski + + PR target/53559 + * config/rs6000/altivec.md (altivec_stvlx): Change machine mode of + operands. + (altivec_stvlxl): Ditto. + (altivec_stvrx): Ditto. + (altivec_stvrxl): Ditto. + 2012-06-04 Vladimir Makarov * ira-int.h (struct target_ira_int): Add member diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index 42e8dd6a9d4..fd4bc9d353b 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -2380,8 +2380,8 @@ (define_insn "altivec_stvlx" [(parallel - [(set (match_operand:V4SI 0 "memory_operand" "=Z") - (match_operand:V4SI 1 "register_operand" "v")) + [(set (match_operand:V16QI 0 "memory_operand" "=Z") + (match_operand:V16QI 1 "register_operand" "v")) (unspec [(const_int 0)] UNSPEC_STVLX)])] "TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL" "stvlx %1,%y0" @@ -2389,8 +2389,8 @@ (define_insn "altivec_stvlxl" [(parallel - [(set (match_operand:V4SI 0 "memory_operand" "=Z") - (match_operand:V4SI 1 "register_operand" "v")) + [(set (match_operand:V16QI 0 "memory_operand" "=Z") + (match_operand:V16QI 1 "register_operand" "v")) (unspec [(const_int 0)] UNSPEC_STVLXL)])] "TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL" "stvlxl %1,%y0" @@ -2398,8 +2398,8 @@ (define_insn "altivec_stvrx" [(parallel - [(set (match_operand:V4SI 0 "memory_operand" "=Z") - (match_operand:V4SI 1 "register_operand" "v")) + [(set (match_operand:V16QI 0 "memory_operand" "=Z") + (match_operand:V16QI 1 "register_operand" "v")) (unspec [(const_int 0)] UNSPEC_STVRX)])] "TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL" "stvrx %1,%y0" @@ -2407,8 +2407,8 @@ (define_insn "altivec_stvrxl" [(parallel - [(set (match_operand:V4SI 0 "memory_operand" "=Z") - (match_operand:V4SI 1 "register_operand" "v")) + [(set (match_operand:V16QI 0 "memory_operand" "=Z") + (match_operand:V16QI 1 "register_operand" "v")) (unspec [(const_int 0)] UNSPEC_STVRXL)])] "TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL" "stvrxl %1,%y0" diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 222f0de9c4a..f9d5e93a607 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,15 @@ +2012-06-04 Edmar Wienskoski + + PR target/53559 + * gcc.target/powerpc/cell_builtin_1.c: New test case. + * gcc.target/powerpc/cell_builtin_2.c: Ditto. + * gcc.target/powerpc/cell_builtin_3.c: Ditto. + * gcc.target/powerpc/cell_builtin_4.c: Ditto. + * gcc.target/powerpc/cell_builtin_5.c: Ditto. + * gcc.target/powerpc/cell_builtin_6.c: Ditto. + * gcc.target/powerpc/cell_builtin_7.c: Ditto. + * gcc.target/powerpc/cell_builtin_8.c: Ditto. + 2012-06-04 Andreas Schwab * g++.dg/debug/dwarf2/nested-3.C: Allow for | comments. diff --git a/gcc/testsuite/gcc.target/powerpc/cell_builtin-1.c b/gcc/testsuite/gcc.target/powerpc/cell_builtin-1.c new file mode 100644 index 00000000000..f2bc7ffb3c4 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/cell_builtin-1.c @@ -0,0 +1,48 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-O2 -maltivec -mcpu=cell" } */ +/* { dg-final { scan-assembler-times "lvlx" 19 } } */ + +#include + +typedef __vector signed char vsc; +typedef __vector signed short vss; +typedef __vector signed int vsi; +typedef __vector unsigned char vuc; +typedef __vector unsigned short vus; +typedef __vector unsigned int vui; +typedef __vector bool char vbc; +typedef __vector bool short vbs; +typedef __vector bool int vbi; +typedef __vector float vsf; +typedef __vector pixel vp; +typedef signed char sc; +typedef signed short ss; +typedef signed int si; +typedef signed long sl; +typedef unsigned char uc; +typedef unsigned short us; +typedef unsigned int ui; +typedef unsigned long ul; +typedef float sf; + +vsc lc1(long a, void *p) { return __builtin_altivec_lvlx (a,p); } +vsf llx01(long a, vsf *p) { return __builtin_vec_lvlx (a,p); } +vsf llx02(long a, sf *p) { return __builtin_vec_lvlx (a,p); } +vbi llx03(long a, vbi *p) { return __builtin_vec_lvlx (a,p); } +vsi llx04(long a, vsi *p) { return __builtin_vec_lvlx (a,p); } +vsi llx05(long a, si *p) { return __builtin_vec_lvlx (a,p); } +vui llx06(long a, vui *p) { return __builtin_vec_lvlx (a,p); } +vui llx07(long a, ui *p) { return __builtin_vec_lvlx (a,p); } +vbs llx08(long a, vbs *p) { return __builtin_vec_lvlx (a,p); } +vp llx09(long a, vp *p) { return __builtin_vec_lvlx (a,p); } +vss llx10(long a, vss *p) { return __builtin_vec_lvlx (a,p); } +vss llx11(long a, ss *p) { return __builtin_vec_lvlx (a,p); } +vus llx12(long a, vus *p) { return __builtin_vec_lvlx (a,p); } +vus llx13(long a, us *p) { return __builtin_vec_lvlx (a,p); } +vbc llx14(long a, vbc *p) { return __builtin_vec_lvlx (a,p); } +vsc llx15(long a, vsc *p) { return __builtin_vec_lvlx (a,p); } +vsc llx16(long a, sc *p) { return __builtin_vec_lvlx (a,p); } +vuc llx17(long a, vuc *p) { return __builtin_vec_lvlx (a,p); } +vuc llx18(long a, uc *p) { return __builtin_vec_lvlx (a,p); } diff --git a/gcc/testsuite/gcc.target/powerpc/cell_builtin-2.c b/gcc/testsuite/gcc.target/powerpc/cell_builtin-2.c new file mode 100644 index 00000000000..220be571659 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/cell_builtin-2.c @@ -0,0 +1,48 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-O2 -maltivec -mcpu=cell" } */ +/* { dg-final { scan-assembler-times "lvlxl" 19 } } */ + +#include + +typedef __vector signed char vsc; +typedef __vector signed short vss; +typedef __vector signed int vsi; +typedef __vector unsigned char vuc; +typedef __vector unsigned short vus; +typedef __vector unsigned int vui; +typedef __vector bool char vbc; +typedef __vector bool short vbs; +typedef __vector bool int vbi; +typedef __vector float vsf; +typedef __vector pixel vp; +typedef signed char sc; +typedef signed short ss; +typedef signed int si; +typedef signed long sl; +typedef unsigned char uc; +typedef unsigned short us; +typedef unsigned int ui; +typedef unsigned long ul; +typedef float sf; + +vsc lc2(long a, void *p) { return __builtin_altivec_lvlxl (a,p); } +vsf llxl01(long a, vsf *p) { return __builtin_vec_lvlxl (a,p); } +vsf llxl02(long a, sf *p) { return __builtin_vec_lvlxl (a,p); } +vbi llxl03(long a, vbi *p) { return __builtin_vec_lvlxl (a,p); } +vsi llxl04(long a, vsi *p) { return __builtin_vec_lvlxl (a,p); } +vsi llxl05(long a, si *p) { return __builtin_vec_lvlxl (a,p); } +vui llxl06(long a, vui *p) { return __builtin_vec_lvlxl (a,p); } +vui llxl07(long a, ui *p) { return __builtin_vec_lvlxl (a,p); } +vbs llxl08(long a, vbs *p) { return __builtin_vec_lvlxl (a,p); } +vp llxl09(long a, vp *p) { return __builtin_vec_lvlxl (a,p); } +vss llxl10(long a, vss *p) { return __builtin_vec_lvlxl (a,p); } +vss llxl11(long a, ss *p) { return __builtin_vec_lvlxl (a,p); } +vus llxl12(long a, vus *p) { return __builtin_vec_lvlxl (a,p); } +vus llxl13(long a, us *p) { return __builtin_vec_lvlxl (a,p); } +vbc llxl14(long a, vbc *p) { return __builtin_vec_lvlxl (a,p); } +vsc llxl15(long a, vsc *p) { return __builtin_vec_lvlxl (a,p); } +vsc llxl16(long a, sc *p) { return __builtin_vec_lvlxl (a,p); } +vuc llxl17(long a, vuc *p) { return __builtin_vec_lvlxl (a,p); } +vuc llxl18(long a, uc *p) { return __builtin_vec_lvlxl (a,p); } diff --git a/gcc/testsuite/gcc.target/powerpc/cell_builtin-3.c b/gcc/testsuite/gcc.target/powerpc/cell_builtin-3.c new file mode 100644 index 00000000000..4b437291ea5 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/cell_builtin-3.c @@ -0,0 +1,48 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-O2 -maltivec -mcpu=cell" } */ +/* { dg-final { scan-assembler-times "lvrx" 19 } } */ + +#include + +typedef __vector signed char vsc; +typedef __vector signed short vss; +typedef __vector signed int vsi; +typedef __vector unsigned char vuc; +typedef __vector unsigned short vus; +typedef __vector unsigned int vui; +typedef __vector bool char vbc; +typedef __vector bool short vbs; +typedef __vector bool int vbi; +typedef __vector float vsf; +typedef __vector pixel vp; +typedef signed char sc; +typedef signed short ss; +typedef signed int si; +typedef signed long sl; +typedef unsigned char uc; +typedef unsigned short us; +typedef unsigned int ui; +typedef unsigned long ul; +typedef float sf; + +vsc lc3(long a, void *p) { return __builtin_altivec_lvrx (a,p); } +vsf lrx01(long a, vsf *p) { return __builtin_vec_lvrx (a,p); } +vsf lrx02(long a, sf *p) { return __builtin_vec_lvrx (a,p); } +vbi lrx03(long a, vbi *p) { return __builtin_vec_lvrx (a,p); } +vsi lrx04(long a, vsi *p) { return __builtin_vec_lvrx (a,p); } +vsi lrx05(long a, si *p) { return __builtin_vec_lvrx (a,p); } +vui lrx06(long a, vui *p) { return __builtin_vec_lvrx (a,p); } +vui lrx07(long a, ui *p) { return __builtin_vec_lvrx (a,p); } +vbs lrx08(long a, vbs *p) { return __builtin_vec_lvrx (a,p); } +vp lrx09(long a, vp *p) { return __builtin_vec_lvrx (a,p); } +vss lrx10(long a, vss *p) { return __builtin_vec_lvrx (a,p); } +vss lrx11(long a, ss *p) { return __builtin_vec_lvrx (a,p); } +vus lrx12(long a, vus *p) { return __builtin_vec_lvrx (a,p); } +vus lrx13(long a, us *p) { return __builtin_vec_lvrx (a,p); } +vbc lrx14(long a, vbc *p) { return __builtin_vec_lvrx (a,p); } +vsc lrx15(long a, vsc *p) { return __builtin_vec_lvrx (a,p); } +vsc lrx16(long a, sc *p) { return __builtin_vec_lvrx (a,p); } +vuc lrx17(long a, vuc *p) { return __builtin_vec_lvrx (a,p); } +vuc lrx18(long a, uc *p) { return __builtin_vec_lvrx (a,p); } diff --git a/gcc/testsuite/gcc.target/powerpc/cell_builtin-4.c b/gcc/testsuite/gcc.target/powerpc/cell_builtin-4.c new file mode 100644 index 00000000000..d73328ac43e --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/cell_builtin-4.c @@ -0,0 +1,48 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-O2 -maltivec -mcpu=cell" } */ +/* { dg-final { scan-assembler-times "lvrxl" 19 } } */ + +#include + +typedef __vector signed char vsc; +typedef __vector signed short vss; +typedef __vector signed int vsi; +typedef __vector unsigned char vuc; +typedef __vector unsigned short vus; +typedef __vector unsigned int vui; +typedef __vector bool char vbc; +typedef __vector bool short vbs; +typedef __vector bool int vbi; +typedef __vector float vsf; +typedef __vector pixel vp; +typedef signed char sc; +typedef signed short ss; +typedef signed int si; +typedef signed long sl; +typedef unsigned char uc; +typedef unsigned short us; +typedef unsigned int ui; +typedef unsigned long ul; +typedef float sf; + +vsc lc4(long a, void *p) { return __builtin_altivec_lvrxl (a,p); } +vsf lrxl01(long a, vsf *p) { return __builtin_vec_lvrxl (a,p); } +vsf lrxl02(long a, sf *p) { return __builtin_vec_lvrxl (a,p); } +vbi lrxl03(long a, vbi *p) { return __builtin_vec_lvrxl (a,p); } +vsi lrxl04(long a, vsi *p) { return __builtin_vec_lvrxl (a,p); } +vsi lrxl05(long a, si *p) { return __builtin_vec_lvrxl (a,p); } +vui lrxl06(long a, vui *p) { return __builtin_vec_lvrxl (a,p); } +vui lrxl07(long a, ui *p) { return __builtin_vec_lvrxl (a,p); } +vbs lrxl08(long a, vbs *p) { return __builtin_vec_lvrxl (a,p); } +vp lrxl09(long a, vp *p) { return __builtin_vec_lvrxl (a,p); } +vss lrxl10(long a, vss *p) { return __builtin_vec_lvrxl (a,p); } +vss lrxl11(long a, ss *p) { return __builtin_vec_lvrxl (a,p); } +vus lrxl12(long a, vus *p) { return __builtin_vec_lvrxl (a,p); } +vus lrxl13(long a, us *p) { return __builtin_vec_lvrxl (a,p); } +vbc lrxl14(long a, vbc *p) { return __builtin_vec_lvrxl (a,p); } +vsc lrxl15(long a, vsc *p) { return __builtin_vec_lvrxl (a,p); } +vsc lrxl16(long a, sc *p) { return __builtin_vec_lvrxl (a,p); } +vuc lrxl17(long a, vuc *p) { return __builtin_vec_lvrxl (a,p); } +vuc lrxl18(long a, uc *p) { return __builtin_vec_lvrxl (a,p); } diff --git a/gcc/testsuite/gcc.target/powerpc/cell_builtin-5.c b/gcc/testsuite/gcc.target/powerpc/cell_builtin-5.c new file mode 100644 index 00000000000..cc6adba8050 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/cell_builtin-5.c @@ -0,0 +1,48 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-O2 -maltivec -mcpu=cell" } */ +/* { dg-final { scan-assembler-times "stvlx" 19 } } */ + +#include + +typedef __vector signed char vsc; +typedef __vector signed short vss; +typedef __vector signed int vsi; +typedef __vector unsigned char vuc; +typedef __vector unsigned short vus; +typedef __vector unsigned int vui; +typedef __vector bool char vbc; +typedef __vector bool short vbs; +typedef __vector bool int vbi; +typedef __vector float vsf; +typedef __vector pixel vp; +typedef signed char sc; +typedef signed short ss; +typedef signed int si; +typedef signed long sl; +typedef unsigned char uc; +typedef unsigned short us; +typedef unsigned int ui; +typedef unsigned long ul; +typedef float sf; + +void sc1(vsc v, long a, void *p) { __builtin_altivec_stvlx (v,a,p); } +void slx01(vsf v, long a, vsf *p) { __builtin_vec_stvlx (v,a,p); } +void slx02(vsf v, long a, sf *p) { __builtin_vec_stvlx (v,a,p); } +void slx03(vbi v, long a, vbi *p) { __builtin_vec_stvlx (v,a,p); } +void slx04(vsi v, long a, vsi *p) { __builtin_vec_stvlx (v,a,p); } +void slx05(vsi v, long a, si *p) { __builtin_vec_stvlx (v,a,p); } +void slx06(vui v, long a, vui *p) { __builtin_vec_stvlx (v,a,p); } +void slx07(vui v, long a, ui *p) { __builtin_vec_stvlx (v,a,p); } +void slx08(vbs v, long a, vbs *p) { __builtin_vec_stvlx (v,a,p); } +void slx09(vp v, long a, vp *p) { __builtin_vec_stvlx (v,a,p); } +void slx10(vss v, long a, vss *p) { __builtin_vec_stvlx (v,a,p); } +void slx11(vss v, long a, ss *p) { __builtin_vec_stvlx (v,a,p); } +void slx12(vus v, long a, vus *p) { __builtin_vec_stvlx (v,a,p); } +void slx13(vus v, long a, us *p) { __builtin_vec_stvlx (v,a,p); } +void slx14(vbc v, long a, vbc *p) { __builtin_vec_stvlx (v,a,p); } +void slx15(vsc v, long a, vsc *p) { __builtin_vec_stvlx (v,a,p); } +void slx16(vsc v, long a, sc *p) { __builtin_vec_stvlx (v,a,p); } +void slx17(vuc v, long a, vuc *p) { __builtin_vec_stvlx (v,a,p); } +void slx18(vuc v, long a, uc *p) { __builtin_vec_stvlx (v,a,p); } diff --git a/gcc/testsuite/gcc.target/powerpc/cell_builtin-6.c b/gcc/testsuite/gcc.target/powerpc/cell_builtin-6.c new file mode 100644 index 00000000000..9c748d973d8 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/cell_builtin-6.c @@ -0,0 +1,48 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-O2 -maltivec -mcpu=cell" } */ +/* { dg-final { scan-assembler-times "stvlxl" 19 } } */ + +#include + +typedef __vector signed char vsc; +typedef __vector signed short vss; +typedef __vector signed int vsi; +typedef __vector unsigned char vuc; +typedef __vector unsigned short vus; +typedef __vector unsigned int vui; +typedef __vector bool char vbc; +typedef __vector bool short vbs; +typedef __vector bool int vbi; +typedef __vector float vsf; +typedef __vector pixel vp; +typedef signed char sc; +typedef signed short ss; +typedef signed int si; +typedef signed long sl; +typedef unsigned char uc; +typedef unsigned short us; +typedef unsigned int ui; +typedef unsigned long ul; +typedef float sf; + +void sc2(vsc v, long a, void *p) { __builtin_altivec_stvlxl (v,a,p); } +void slxl01(vsf v, long a, vsf *p) { __builtin_vec_stvlxl (v,a,p); } +void slxl02(vsf v, long a, sf *p) { __builtin_vec_stvlxl (v,a,p); } +void slxl03(vbi v, long a, vbi *p) { __builtin_vec_stvlxl (v,a,p); } +void slxl04(vsi v, long a, vsi *p) { __builtin_vec_stvlxl (v,a,p); } +void slxl05(vsi v, long a, si *p) { __builtin_vec_stvlxl (v,a,p); } +void slxl06(vui v, long a, vui *p) { __builtin_vec_stvlxl (v,a,p); } +void slxl07(vui v, long a, ui *p) { __builtin_vec_stvlxl (v,a,p); } +void slxl08(vbs v, long a, vbs *p) { __builtin_vec_stvlxl (v,a,p); } +void slxl09(vp v, long a, vp *p) { __builtin_vec_stvlxl (v,a,p); } +void slxl10(vss v, long a, vss *p) { __builtin_vec_stvlxl (v,a,p); } +void slxl11(vss v, long a, ss *p) { __builtin_vec_stvlxl (v,a,p); } +void slxl12(vus v, long a, vus *p) { __builtin_vec_stvlxl (v,a,p); } +void slxl13(vus v, long a, us *p) { __builtin_vec_stvlxl (v,a,p); } +void slxl14(vbc v, long a, vbc *p) { __builtin_vec_stvlxl (v,a,p); } +void slxl15(vsc v, long a, vsc *p) { __builtin_vec_stvlxl (v,a,p); } +void slxl16(vsc v, long a, sc *p) { __builtin_vec_stvlxl (v,a,p); } +void slxl17(vuc v, long a, vuc *p) { __builtin_vec_stvlxl (v,a,p); } +void slxl18(vuc v, long a, uc *p) { __builtin_vec_stvlxl (v,a,p); } diff --git a/gcc/testsuite/gcc.target/powerpc/cell_builtin-7.c b/gcc/testsuite/gcc.target/powerpc/cell_builtin-7.c new file mode 100644 index 00000000000..abdb3b0caf1 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/cell_builtin-7.c @@ -0,0 +1,48 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-O2 -maltivec -mcpu=cell" } */ +/* { dg-final { scan-assembler-times "stvrx" 19 } } */ + +#include + +typedef __vector signed char vsc; +typedef __vector signed short vss; +typedef __vector signed int vsi; +typedef __vector unsigned char vuc; +typedef __vector unsigned short vus; +typedef __vector unsigned int vui; +typedef __vector bool char vbc; +typedef __vector bool short vbs; +typedef __vector bool int vbi; +typedef __vector float vsf; +typedef __vector pixel vp; +typedef signed char sc; +typedef signed short ss; +typedef signed int si; +typedef signed long sl; +typedef unsigned char uc; +typedef unsigned short us; +typedef unsigned int ui; +typedef unsigned long ul; +typedef float sf; + +void sc3(vsc v, long a, void *p) { __builtin_altivec_stvrx (v,a,p); } +void srx01(vsf v, long a, vsf *p) { __builtin_vec_stvrx (v,a,p); } +void srx02(vsf v, long a, sf *p) { __builtin_vec_stvrx (v,a,p); } +void srx03(vbi v, long a, vbi *p) { __builtin_vec_stvrx (v,a,p); } +void srx04(vsi v, long a, vsi *p) { __builtin_vec_stvrx (v,a,p); } +void srx05(vsi v, long a, si *p) { __builtin_vec_stvrx (v,a,p); } +void srx06(vui v, long a, vui *p) { __builtin_vec_stvrx (v,a,p); } +void srx07(vui v, long a, ui *p) { __builtin_vec_stvrx (v,a,p); } +void srx08(vbs v, long a, vbs *p) { __builtin_vec_stvrx (v,a,p); } +void srx09(vp v, long a, vp *p) { __builtin_vec_stvrx (v,a,p); } +void srx10(vss v, long a, vss *p) { __builtin_vec_stvrx (v,a,p); } +void srx11(vss v, long a, ss *p) { __builtin_vec_stvrx (v,a,p); } +void srx12(vus v, long a, vus *p) { __builtin_vec_stvrx (v,a,p); } +void srx13(vus v, long a, us *p) { __builtin_vec_stvrx (v,a,p); } +void srx14(vbc v, long a, vbc *p) { __builtin_vec_stvrx (v,a,p); } +void srx15(vsc v, long a, vsc *p) { __builtin_vec_stvrx (v,a,p); } +void srx16(vsc v, long a, sc *p) { __builtin_vec_stvrx (v,a,p); } +void srx17(vuc v, long a, vuc *p) { __builtin_vec_stvrx (v,a,p); } +void srx18(vuc v, long a, uc *p) { __builtin_vec_stvrx (v,a,p); } diff --git a/gcc/testsuite/gcc.target/powerpc/cell_builtin-8.c b/gcc/testsuite/gcc.target/powerpc/cell_builtin-8.c new file mode 100644 index 00000000000..ec7fc3031b4 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/cell_builtin-8.c @@ -0,0 +1,48 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-O2 -maltivec -mcpu=cell" } */ +/* { dg-final { scan-assembler-times "stvrxl" 19 } } */ + +#include + +typedef __vector signed char vsc; +typedef __vector signed short vss; +typedef __vector signed int vsi; +typedef __vector unsigned char vuc; +typedef __vector unsigned short vus; +typedef __vector unsigned int vui; +typedef __vector bool char vbc; +typedef __vector bool short vbs; +typedef __vector bool int vbi; +typedef __vector float vsf; +typedef __vector pixel vp; +typedef signed char sc; +typedef signed short ss; +typedef signed int si; +typedef signed long sl; +typedef unsigned char uc; +typedef unsigned short us; +typedef unsigned int ui; +typedef unsigned long ul; +typedef float sf; + +void sc4(vsc v, long a, void *p) { __builtin_altivec_stvrxl (v,a,p); } +void srxl01(vsf v, long a, vsf *p) { __builtin_vec_stvrxl (v,a,p); } +void srxl02(vsf v, long a, sf *p) { __builtin_vec_stvrxl (v,a,p); } +void srxl03(vbi v, long a, vbi *p) { __builtin_vec_stvrxl (v,a,p); } +void srxl04(vsi v, long a, vsi *p) { __builtin_vec_stvrxl (v,a,p); } +void srxl05(vsi v, long a, si *p) { __builtin_vec_stvrxl (v,a,p); } +void srxl06(vui v, long a, vui *p) { __builtin_vec_stvrxl (v,a,p); } +void srxl07(vui v, long a, ui *p) { __builtin_vec_stvrxl (v,a,p); } +void srxl08(vbs v, long a, vbs *p) { __builtin_vec_stvrxl (v,a,p); } +void srxl09(vp v, long a, vp *p) { __builtin_vec_stvrxl (v,a,p); } +void srxl10(vss v, long a, vss *p) { __builtin_vec_stvrxl (v,a,p); } +void srxl11(vss v, long a, ss *p) { __builtin_vec_stvrxl (v,a,p); } +void srxl12(vus v, long a, vus *p) { __builtin_vec_stvrxl (v,a,p); } +void srxl13(vus v, long a, us *p) { __builtin_vec_stvrxl (v,a,p); } +void srxl14(vbc v, long a, vbc *p) { __builtin_vec_stvrxl (v,a,p); } +void srxl15(vsc v, long a, vsc *p) { __builtin_vec_stvrxl (v,a,p); } +void srxl16(vsc v, long a, sc *p) { __builtin_vec_stvrxl (v,a,p); } +void srxl17(vuc v, long a, vuc *p) { __builtin_vec_stvrxl (v,a,p); } +void srxl18(vuc v, long a, uc *p) { __builtin_vec_stvrxl (v,a,p); } -- 2.30.2