From fbc9ba7559b15d29cd8dc38dfb3751845ef3fd37 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Nicolai=20H=C3=A4hnle?= Date: Wed, 20 Jul 2016 21:30:56 +0200 Subject: [PATCH] amdgpu/addrlib: Pad pitch to multiples of 256 for DCC surface on Fiji The change also modifies function CiLib::HwlPadDimensions to report adjusted pitch alignment. --- src/amd/addrlib/core/addrlib1.cpp | 12 +++--- src/amd/addrlib/core/addrlib1.h | 10 +++-- src/amd/addrlib/r800/ciaddrlib.cpp | 66 ++++++++++++++++++++++------- src/amd/addrlib/r800/ciaddrlib.h | 11 +++-- src/amd/addrlib/r800/egbaddrlib.cpp | 25 +++-------- src/amd/addrlib/r800/egbaddrlib.h | 8 ++++ src/amd/addrlib/r800/siaddrlib.cpp | 42 ++++++++++++++++++ src/amd/addrlib/r800/siaddrlib.h | 6 +++ 8 files changed, 131 insertions(+), 49 deletions(-) diff --git a/src/amd/addrlib/core/addrlib1.cpp b/src/amd/addrlib/core/addrlib1.cpp index d48aa7c92bf..040891c431c 100644 --- a/src/amd/addrlib/core/addrlib1.cpp +++ b/src/amd/addrlib/core/addrlib1.cpp @@ -3228,13 +3228,14 @@ VOID Lib::PadDimensions( UINT_32 padDims, ///< [in] Dimensions to pad valid value 1,2,3 UINT_32 mipLevel, ///< [in] MipLevel UINT_32* pPitch, ///< [in,out] pitch in pixels - UINT_32 pitchAlign, ///< [in] pitch alignment + UINT_32* pPitchAlign, ///< [in,out] pitch align could be changed in HwlPadDimensions UINT_32* pHeight, ///< [in,out] height in pixels UINT_32 heightAlign, ///< [in] height alignment UINT_32* pSlices, ///< [in,out] number of slices UINT_32 sliceAlign ///< [in] number of slice alignment ) const { + UINT_32 pitchAlign = *pPitchAlign; UINT_32 thickness = Thickness(tileMode); ADDR_ASSERT(padDims <= 3); @@ -3302,14 +3303,11 @@ VOID Lib::PadDimensions( flags, numSamples, pTileInfo, - padDims, mipLevel, pPitch, - pitchAlign, - pHeight, - heightAlign, - pSlices, - sliceAlign); + pPitchAlign, + *pHeight, + heightAlign); } diff --git a/src/amd/addrlib/core/addrlib1.h b/src/amd/addrlib/core/addrlib1.h index 9c66f53e737..c1fc693b64f 100644 --- a/src/amd/addrlib/core/addrlib1.h +++ b/src/amd/addrlib/core/addrlib1.h @@ -71,6 +71,9 @@ struct TileModeFlags UINT_32 isBankSwapped : 1; }; +static const UINT_32 Block64K = 0x10000; +static const UINT_32 PrtTileSize = Block64K; + /** **************************************************************************************************** * @brief This class contains asic independent address lib functionalities @@ -365,14 +368,13 @@ protected: VOID PadDimensions( AddrTileMode tileMode, UINT_32 bpp, ADDR_SURFACE_FLAGS flags, UINT_32 numSamples, ADDR_TILEINFO* pTileInfo, UINT_32 padDims, UINT_32 mipLevel, - UINT_32* pPitch, UINT_32 pitchAlign, UINT_32* pHeight, UINT_32 heightAlign, + UINT_32* pPitch, UINT_32* pPitchAlign, UINT_32* pHeight, UINT_32 heightAlign, UINT_32* pSlices, UINT_32 sliceAlign) const; virtual VOID HwlPadDimensions( AddrTileMode tileMode, UINT_32 bpp, ADDR_SURFACE_FLAGS flags, - UINT_32 numSamples, ADDR_TILEINFO* pTileInfo, UINT_32 padDims, UINT_32 mipLevel, - UINT_32* pPitch, UINT_32 pitchAlign, UINT_32* pHeight, UINT_32 heightAlign, - UINT_32* pSlices, UINT_32 sliceAlign) const + UINT_32 numSamples, ADDR_TILEINFO* pTileInfo, UINT_32 mipLevel, + UINT_32* pPitch, UINT_32* pPitchAlign, UINT_32 height, UINT_32 heightAlign) const { } diff --git a/src/amd/addrlib/r800/ciaddrlib.cpp b/src/amd/addrlib/r800/ciaddrlib.cpp index 3986c3b2998..3509024f76f 100644 --- a/src/amd/addrlib/r800/ciaddrlib.cpp +++ b/src/amd/addrlib/r800/ciaddrlib.cpp @@ -1939,6 +1939,41 @@ UINT_64 CiLib::HwlComputeMetadataNibbleAddress( return metadataAddress; } +/** +**************************************************************************************************** +* CiLib::HwlComputeSurfaceAlignmentsMacroTiled +* +* @brief +* Hardware layer function to compute alignment request for macro tile mode +* +* @return +* N/A +* +**************************************************************************************************** +*/ +VOID CiLib::HwlComputeSurfaceAlignmentsMacroTiled( + AddrTileMode tileMode, ///< [in] tile mode + UINT_32 bpp, ///< [in] bits per pixel + ADDR_SURFACE_FLAGS flags, ///< [in] surface flags + UINT_32 mipLevel, ///< [in] mip level + UINT_32 numSamples, ///< [in] number of samples + ADDR_TILEINFO* pTileInfo, ///< [in,out] bank structure. + UINT_32* pBaseAlign, ///< [out] base address alignment in bytes + UINT_32* pPitchAlign, ///< [out] pitch alignment in pixels + UINT_32* pHeightAlign, ///< [out] height alignment in pixels + UINT_32* pMacroTileWidth, ///< [out] macro tile width in pixels + UINT_32* pMacroTileHeight ///< [out] macro tile height in pixels + ) const +{ + if ((m_settings.isFiji == TRUE) && + (flags.dccCompatible == TRUE) && + (mipLevel == 0) && + (tileMode == ADDR_TM_PRT_TILED_THIN1)) + { + *pPitchAlign = PowTwoAlign(*pPitchAlign, 256); + } +} + /** **************************************************************************************************** * CiLib::HwlPadDimensions @@ -1956,22 +1991,19 @@ VOID CiLib::HwlPadDimensions( UINT_32 bpp, ///< [in] bits per pixel ADDR_SURFACE_FLAGS flags, ///< [in] surface flags UINT_32 numSamples, ///< [in] number of samples - ADDR_TILEINFO* pTileInfo, ///< [in,out] bank structure. - UINT_32 padDims, ///< [in] Dimensions to pad valid value 1,2,3 - UINT_32 mipLevel, ///< [in] MipLevel + ADDR_TILEINFO* pTileInfo, ///< [in] tile info + UINT_32 mipLevel, ///< [in] mip level UINT_32* pPitch, ///< [in,out] pitch in pixels - UINT_32 pitchAlign, ///< [in] pitch alignment - UINT_32* pHeight, ///< [in,out] height in pixels - UINT_32 heightAlign, ///< [in] height alignment - UINT_32* pSlices, ///< [in,out] number of slices - UINT_32 sliceAlign ///< [in] number of slice alignment + UINT_32* pPitchAlign, ///< [in,out] pitch alignment + UINT_32 height, ///< [in] height in pixels + UINT_32 heightAlign ///< [in] height alignment ) const { - if (m_settings.isVolcanicIslands && - flags.dccCompatible && + if ((m_settings.isVolcanicIslands == TRUE) && + (flags.dccCompatible == TRUE) && (numSamples > 1) && (mipLevel == 0) && - IsMacroTiled(tileMode)) + (IsMacroTiled(tileMode) == TRUE)) { UINT_32 tileSizePerSample = BITS_TO_BYTES(bpp * MicroTileWidth * MicroTileHeight); UINT_32 samplesPerSplit = pTileInfo->tileSplitBytes / tileSizePerSample; @@ -1979,7 +2011,7 @@ VOID CiLib::HwlPadDimensions( if (samplesPerSplit < numSamples) { UINT_32 dccFastClearByteAlign = HwlGetPipes(pTileInfo) * m_pipeInterleaveBytes * 256; - UINT_32 bytesPerSplit = BITS_TO_BYTES((*pPitch) * (*pHeight) * bpp * samplesPerSplit); + UINT_32 bytesPerSplit = BITS_TO_BYTES((*pPitch) * height * bpp * samplesPerSplit); ADDR_ASSERT(IsPow2(dccFastClearByteAlign)); @@ -1988,15 +2020,14 @@ VOID CiLib::HwlPadDimensions( UINT_32 dccFastClearPixelAlign = dccFastClearByteAlign / BITS_TO_BYTES(bpp) / samplesPerSplit; - UINT_32 macroTilePixelAlign = pitchAlign * heightAlign; + UINT_32 macroTilePixelAlign = (*pPitchAlign) * heightAlign; if ((dccFastClearPixelAlign >= macroTilePixelAlign) && ((dccFastClearPixelAlign % macroTilePixelAlign) == 0)) { UINT_32 dccFastClearPitchAlignInMacroTile = dccFastClearPixelAlign / macroTilePixelAlign; - UINT_32 heightInMacroTile = *pHeight / heightAlign; - UINT_32 dccFastClearPitchAlignInPixels; + UINT_32 heightInMacroTile = height / heightAlign; while ((heightInMacroTile > 1) && ((heightInMacroTile % 2) == 0) && @@ -2007,7 +2038,8 @@ VOID CiLib::HwlPadDimensions( dccFastClearPitchAlignInMacroTile >>= 1; } - dccFastClearPitchAlignInPixels = pitchAlign * dccFastClearPitchAlignInMacroTile; + UINT_32 dccFastClearPitchAlignInPixels = + (*pPitchAlign) * dccFastClearPitchAlignInMacroTile; if (IsPow2(dccFastClearPitchAlignInPixels)) { @@ -2019,6 +2051,8 @@ VOID CiLib::HwlPadDimensions( *pPitch /= dccFastClearPitchAlignInPixels; *pPitch *= dccFastClearPitchAlignInPixels; } + + *pPitchAlign = dccFastClearPitchAlignInPixels; } } } diff --git a/src/amd/addrlib/r800/ciaddrlib.h b/src/amd/addrlib/r800/ciaddrlib.h index a9b1607ff1d..c59a0b127a1 100644 --- a/src/amd/addrlib/r800/ciaddrlib.h +++ b/src/amd/addrlib/r800/ciaddrlib.h @@ -166,9 +166,14 @@ protected: virtual VOID HwlPadDimensions( AddrTileMode tileMode, UINT_32 bpp, ADDR_SURFACE_FLAGS flags, - UINT_32 numSamples, ADDR_TILEINFO* pTileInfo, UINT_32 padDims, UINT_32 mipLevel, - UINT_32* pPitch, UINT_32 pitchAlign, UINT_32* pHeight, UINT_32 heightAlign, - UINT_32* pSlices, UINT_32 sliceAlign) const; + UINT_32 numSamples, ADDR_TILEINFO* pTileInfo, UINT_32 mipLevel, + UINT_32* pPitch, UINT_32 *PitchAlign, UINT_32 height, UINT_32 heightAlign) const; + + virtual VOID HwlComputeSurfaceAlignmentsMacroTiled( + AddrTileMode tileMode, UINT_32 bpp, ADDR_SURFACE_FLAGS flags, + UINT_32 mipLevel, UINT_32 numSamples, ADDR_TILEINFO* pTileInfo, + UINT_32* pBaseAlign, UINT_32* pPitchAlign, UINT_32* pHeightAlign, + UINT_32* pMacroTileWidth, UINT_32* pMacroTileHeight) const; private: VOID ReadGbTileMode( diff --git a/src/amd/addrlib/r800/egbaddrlib.cpp b/src/amd/addrlib/r800/egbaddrlib.cpp index b15168263f3..9655c47f7a8 100644 --- a/src/amd/addrlib/r800/egbaddrlib.cpp +++ b/src/amd/addrlib/r800/egbaddrlib.cpp @@ -264,7 +264,7 @@ BOOL_32 EgBasedLib::ComputeSurfaceInfoLinear( pOut->pTileInfo, padDims, pIn->mipLevel, - &expPitch, pOut->pitchAlign, + &expPitch, &pOut->pitchAlign, &expHeight, pOut->heightAlign, &expNumSlices, microTileThickness); @@ -378,7 +378,7 @@ BOOL_32 EgBasedLib::ComputeSurfaceInfoMicroTiled( pOut->pTileInfo, padDims, pIn->mipLevel, - &expPitch, pOut->pitchAlign, + &expPitch, &pOut->pitchAlign, &expHeight, pOut->heightAlign, &expNumSlices, microTileThickness); @@ -527,7 +527,7 @@ BOOL_32 EgBasedLib::ComputeSurfaceInfoMacroTiled( pOut->pTileInfo, padDims, pIn->mipLevel, - &paddedPitch, pOut->pitchAlign, + &paddedPitch, &pOut->pitchAlign, &paddedHeight, pOut->heightAlign, &expNumSlices, microTileThickness); @@ -932,22 +932,9 @@ BOOL_32 EgBasedLib::ComputeSurfaceAlignmentsMacroTiled( *pBaseAlign = pipes * pTileInfo->bankWidth * pTileInfo->banks * pTileInfo->bankHeight * tileSize; - if ((mipLevel == 0) && (flags.prt) && (m_chipFamily == ADDR_CHIP_FAMILY_SI)) - { - static const UINT_32 PrtTileSize = 0x10000; - - UINT_32 macroTileSize = macroTileWidth * macroTileHeight * numSamples * bpp / 8; - - if (macroTileSize < PrtTileSize) - { - UINT_32 numMacroTiles = PrtTileSize / macroTileSize; - - ADDR_ASSERT((PrtTileSize % macroTileSize) == 0); - - *pPitchAlign *= numMacroTiles; - *pBaseAlign *= numMacroTiles; - } - } + HwlComputeSurfaceAlignmentsMacroTiled(tileMode, bpp, flags, mipLevel, numSamples, + pTileInfo, pBaseAlign, pPitchAlign, pHeightAlign, + pMacroTileWidth, pMacroTileHeight); } return valid; diff --git a/src/amd/addrlib/r800/egbaddrlib.h b/src/amd/addrlib/r800/egbaddrlib.h index c397cfc4f81..1a560033681 100644 --- a/src/amd/addrlib/r800/egbaddrlib.h +++ b/src/amd/addrlib/r800/egbaddrlib.h @@ -300,6 +300,14 @@ protected: static UINT_32 ComputeFmaskNumPlanesFromNumSamples(UINT_32 numSamples); static UINT_32 ComputeFmaskResolvedBppFromNumSamples(UINT_32 numSamples); + virtual VOID HwlComputeSurfaceAlignmentsMacroTiled( + AddrTileMode tileMode, UINT_32 bpp, ADDR_SURFACE_FLAGS flags, + UINT_32 mipLevel, UINT_32 numSamples, ADDR_TILEINFO* pTileInfo, + UINT_32* pBaseAlign, UINT_32* pPitchAlign, UINT_32* pHeightAlign, + UINT_32* pMacroTileWidth, UINT_32* pMacroTileHeight) const + { + } + private: BOOL_32 ComputeSurfaceInfoLinear( diff --git a/src/amd/addrlib/r800/siaddrlib.cpp b/src/amd/addrlib/r800/siaddrlib.cpp index 512fb273243..f8f937950ed 100644 --- a/src/amd/addrlib/r800/siaddrlib.cpp +++ b/src/amd/addrlib/r800/siaddrlib.cpp @@ -3325,6 +3325,48 @@ ADDR_E_RETURNCODE SiLib::HwlGetMaxAlignments( return ADDR_OK; } +/** +**************************************************************************************************** +* SiLib::HwlComputeSurfaceAlignmentsMacroTiled +* +* @brief +* Hardware layer function to compute alignment request for macro tile mode +* +* @return +* N/A +* +**************************************************************************************************** +*/ +VOID SiLib::HwlComputeSurfaceAlignmentsMacroTiled( + AddrTileMode tileMode, ///< [in] tile mode + UINT_32 bpp, ///< [in] bits per pixel + ADDR_SURFACE_FLAGS flags, ///< [in] surface flags + UINT_32 mipLevel, ///< [in] mip level + UINT_32 numSamples, ///< [in] number of samples + ADDR_TILEINFO* pTileInfo, ///< [in,out] bank structure. + UINT_32* pBaseAlign, ///< [out] base address alignment in bytes + UINT_32* pPitchAlign, ///< [out] pitch alignment in pixels + UINT_32* pHeightAlign, ///< [out] height alignment in pixels + UINT_32* pMacroTileWidth, ///< [out] macro tile width in pixels + UINT_32* pMacroTileHeight ///< [out] macro tile height in pixels + ) const +{ + if ((mipLevel == 0) && (flags.prt)) + { + UINT_32 macroTileSize = (*pMacroTileWidth) * (*pMacroTileHeight) * numSamples * bpp / 8; + + if (macroTileSize < PrtTileSize) + { + UINT_32 numMacroTiles = PrtTileSize / macroTileSize; + + ADDR_ASSERT((PrtTileSize % macroTileSize) == 0); + + *pPitchAlign *= numMacroTiles; + *pBaseAlign *= numMacroTiles; + } + } +} + /** **************************************************************************************************** * SiLib::InitEquationTable diff --git a/src/amd/addrlib/r800/siaddrlib.h b/src/amd/addrlib/r800/siaddrlib.h index b63d7e878dc..c40b5460b4f 100644 --- a/src/amd/addrlib/r800/siaddrlib.h +++ b/src/amd/addrlib/r800/siaddrlib.h @@ -241,6 +241,12 @@ protected: virtual ADDR_E_RETURNCODE HwlGetMaxAlignments(ADDR_GET_MAX_ALINGMENTS_OUTPUT* pOut) const; + virtual VOID HwlComputeSurfaceAlignmentsMacroTiled( + AddrTileMode tileMode, UINT_32 bpp, ADDR_SURFACE_FLAGS flags, + UINT_32 mipLevel, UINT_32 numSamples, ADDR_TILEINFO* pTileInfo, + UINT_32* pBaseAlign, UINT_32* pPitchAlign, UINT_32* pHeightAlign, + UINT_32* pMacroTileWidth, UINT_32* pMacroTileHeight) const; + // Get equation table pointer and number of equations virtual UINT_32 HwlGetEquationTableInfo(const ADDR_EQUATION** ppEquationTable) const { -- 2.30.2