From fbcdf880ee23a57ab2bcd5ab796171cdab4f73a1 Mon Sep 17 00:00:00 2001 From: Xianwei Zhang Date: Fri, 4 May 2018 17:44:30 -0400 Subject: [PATCH] arch-gcn3: Implement instruction v_div_scale_f32 Instruction v_div_scale_f32 was unimplemented, the implementation was added by mimicking v_div_scale_f64. Change-Id: I89cdfd02ab01b5936de0e9f6c41e7f3fc4f10ae1 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29919 Reviewed-by: Anthony Gutierrez Reviewed-by: Xianwei Zhang Maintainer: Anthony Gutierrez Tested-by: kokoro --- src/arch/gcn3/insts/instructions.cc | 36 +++++++++++++++++++++++++++-- 1 file changed, 34 insertions(+), 2 deletions(-) diff --git a/src/arch/gcn3/insts/instructions.cc b/src/arch/gcn3/insts/instructions.cc index 8d63296bf..bd6e4f44e 100644 --- a/src/arch/gcn3/insts/instructions.cc +++ b/src/arch/gcn3/insts/instructions.cc @@ -28746,8 +28746,40 @@ namespace Gcn3ISA void Inst_VOP3__V_DIV_SCALE_F32::execute(GPUDynInstPtr gpuDynInst) { - panicUnimplemented(); - } + Wavefront *wf = gpuDynInst->wavefront(); + ConstVecOperandF32 src0(gpuDynInst, extData.SRC0); + ConstVecOperandF32 src1(gpuDynInst, extData.SRC1); + ConstVecOperandF32 src2(gpuDynInst, extData.SRC2); + ScalarOperandU64 vcc(gpuDynInst, instData.SDST); + VecOperandF32 vdst(gpuDynInst, instData.VDST); + + src0.readSrc(); + src1.readSrc(); + src2.readSrc(); + + if (extData.NEG & 0x1) { + src0.negModifier(); + } + + if (extData.NEG & 0x2) { + src1.negModifier(); + } + + if (extData.NEG & 0x4) { + src2.negModifier(); + } + + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { + if (wf->execMask(lane)) { + vdst[lane] = src0[lane]; + vcc.setBit(lane, 0); + } + } + + vcc.write(); + vdst.write(); + } // execute + // --- Inst_VOP3__V_DIV_SCALE_F64 class methods --- Inst_VOP3__V_DIV_SCALE_F64::Inst_VOP3__V_DIV_SCALE_F64( InFmt_VOP3_SDST_ENC *iFmt) -- 2.30.2