From fbf80938215fcfc28c990849a93c2c7eba9a84d3 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 5 Jun 2021 12:53:26 +0000 Subject: [PATCH] more comments --- experiments9/tsmc_c018/doDesign.py | 1 + 1 file changed, 1 insertion(+) diff --git a/experiments9/tsmc_c018/doDesign.py b/experiments9/tsmc_c018/doDesign.py index 6e90700..fa6c081 100644 --- a/experiments9/tsmc_c018/doDesign.py +++ b/experiments9/tsmc_c018/doDesign.py @@ -229,6 +229,7 @@ def scriptMain (**kw): ls180Conf.chipSize = (coreSizeX + chipBorder + u(5.0), coreSizeY + chipBorder - u(0.04) ) #ls180Conf.useHTree( 'core.subckt_12941_test_issuer.ti_coresync_clk' ) # XXX this is probably just por_clk not core.por_clk + # or, more likely, core.pllclk_clk ls180Conf.useHTree( 'core.por_clk' ) ls180Conf.useHTree( 'jtag_tck_from_pad' ) -- 2.30.2