From fc256a3df6502d725131a3aa979c2a88aa695d3d Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 19 Jul 2020 15:53:36 +0100 Subject: [PATCH] fix bug in alu_fsm.py found by cxxsim: missing one cycle hold of ready_i --- src/soc/experiment/alu_fsm.py | 11 ++++++++--- src/soc/fu/alu/test/test_pipe_caller.py | 2 +- 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/src/soc/experiment/alu_fsm.py b/src/soc/experiment/alu_fsm.py index f85703c8..b3ab5b17 100644 --- a/src/soc/experiment/alu_fsm.py +++ b/src/soc/experiment/alu_fsm.py @@ -17,7 +17,11 @@ The basic rules are: """ from nmigen import Elaboratable, Signal, Module, Cat -from nmigen.back.pysim import Simulator +cxxsim = False +if cxxsim: + from nmigen.sim.cxxsim import Simulator, Settle +else: + from nmigen.back.pysim import Simulator, Settle from nmigen.cli import rtlil from math import log2 from nmutil.iocontrol import PrevControl, NextControl @@ -236,6 +240,9 @@ def test_shifter(): yield # read result result = yield dut.n.data_o.data + + # must leave ready_i valid for 1 cycle, ready_i to register for 1 cycle + yield # negate n.ready_i yield dut.n.ready_i.eq(0) # check result @@ -263,8 +270,6 @@ def test_shifter(): sim.add_sync_process(consumer) sim_writer = sim.write_vcd( "test_shifter.vcd", - "test_shifter.gtkw", - traces=dut.ports() ) with sim_writer: sim.run() diff --git a/src/soc/fu/alu/test/test_pipe_caller.py b/src/soc/fu/alu/test/test_pipe_caller.py index 88b61b70..b2233ca8 100644 --- a/src/soc/fu/alu/test/test_pipe_caller.py +++ b/src/soc/fu/alu/test/test_pipe_caller.py @@ -1,6 +1,6 @@ from nmigen import Module, Signal from nmigen.back.pysim import Delay, Settle -cxxsim = False +cxxsim = True if cxxsim: from nmigen.sim.cxxsim import Simulator else: -- 2.30.2