From fc3187317b0ef60cc1510f4607f781aa8e8465c5 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Mon, 10 Sep 2012 23:46:19 +0200 Subject: [PATCH] examples: demonstrate multi-clock support --- examples/basic/memory.py | 2 +- examples/basic/psync.py | 23 +++++++++++++++++++++++ 2 files changed, 24 insertions(+), 1 deletion(-) create mode 100644 examples/basic/psync.py diff --git a/examples/basic/memory.py b/examples/basic/memory.py index ec61c83a..30d0430c 100644 --- a/examples/basic/memory.py +++ b/examples/basic/memory.py @@ -15,7 +15,7 @@ p1 = MemoryPort(a1, d1, we1, dw1, we_granularity=8) a2 = Signal(BV(d_b)) d2 = Signal(BV(w)) re2 = Signal() -p2 = MemoryPort(a2, d2, re=re2) +p2 = MemoryPort(a2, d2, re=re2, clock_domain="rd") mem = Memory(w, d, p1, p2, init=[5, 18, 32]) f = Fragment(memories=[mem]) diff --git a/examples/basic/psync.py b/examples/basic/psync.py new file mode 100644 index 00000000..4ca25f5d --- /dev/null +++ b/examples/basic/psync.py @@ -0,0 +1,23 @@ +from migen.fhdl.structure import * +from migen.fhdl import verilog + +# convert pulse into level change +i = Signal() +level = Signal() +isync = [If(i, level.eq(~level))] + +# synchronize level to oclk domain +slevel = [Signal() for i in range(3)] +osync = [ + slevel[0].eq(level), + slevel[1].eq(slevel[0]), + slevel[2].eq(slevel[1]) +] + +# regenerate pulse +o = Signal() +comb = [o.eq(slevel[1] ^ slevel[2])] + +f = Fragment(comb, {"i": isync, "o": osync}) +v = verilog.convert(f, ios={i, o}) +print(v) -- 2.30.2