From fc3832dfaaca3f4d830ff9a18dbeb0856fcacaf9 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Tiago=20M=C3=BCck?= Date: Thu, 27 Aug 2020 20:05:48 -0500 Subject: [PATCH] mem-ruby: add wakeup_port statement MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit While the wakeUpBuffers/wakeUpAllBuffers check all message buffers, wakeup_port wakes up only the messages stalled on the specified port and address. Usage is the same as the stall_and_wait statement, e.g.: wakeup_port(reqInPort, addr); Change-Id: I57dc77d574c0016ca55786ce16a73061a1d37f2e Signed-off-by: Tiago Mück Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41155 Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power Tested-by: kokoro --- .../slicc_interface/AbstractController.cc | 24 +++++++- .../slicc_interface/AbstractController.hh | 3 +- src/mem/slicc/ast/WakeupPortStatementAST.py | 55 +++++++++++++++++++ src/mem/slicc/ast/__init__.py | 13 +++++ src/mem/slicc/parser.py | 7 ++- 5 files changed, 99 insertions(+), 3 deletions(-) create mode 100644 src/mem/slicc/ast/WakeupPortStatementAST.py diff --git a/src/mem/ruby/slicc_interface/AbstractController.cc b/src/mem/ruby/slicc_interface/AbstractController.cc index b7da81e14..d39d0fbdf 100644 --- a/src/mem/ruby/slicc_interface/AbstractController.cc +++ b/src/mem/ruby/slicc_interface/AbstractController.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017,2019,2020 ARM Limited + * Copyright (c) 2017,2019-2021 ARM Limited * All rights reserved. * * The license below extends only to copyright in the software and shall @@ -142,6 +142,28 @@ AbstractController::stallBuffer(MessageBuffer* buf, Addr addr) (*(m_waiting_buffers[addr]))[m_cur_in_port] = buf; } +void +AbstractController::wakeUpBuffer(MessageBuffer* buf, Addr addr) +{ + auto iter = m_waiting_buffers.find(addr); + if (iter != m_waiting_buffers.end()) { + bool has_other_msgs = false; + MsgVecType* msgVec = iter->second; + for (unsigned int port = 0; port < msgVec->size(); ++port) { + if ((*msgVec)[port] == buf) { + buf->reanalyzeMessages(addr, clockEdge()); + (*msgVec)[port] = NULL; + } else if ((*msgVec)[port] != NULL) { + has_other_msgs = true; + } + } + if (!has_other_msgs) { + delete msgVec; + m_waiting_buffers.erase(iter); + } + } +} + void AbstractController::wakeUpBuffers(Addr addr) { diff --git a/src/mem/ruby/slicc_interface/AbstractController.hh b/src/mem/ruby/slicc_interface/AbstractController.hh index 78ea38c74..214b07236 100644 --- a/src/mem/ruby/slicc_interface/AbstractController.hh +++ b/src/mem/ruby/slicc_interface/AbstractController.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017,2019,2020 ARM Limited + * Copyright (c) 2017,2019-2021 ARM Limited * All rights reserved. * * The license below extends only to copyright in the software and shall @@ -270,6 +270,7 @@ class AbstractController : public ClockedObject, public Consumer } void stallBuffer(MessageBuffer* buf, Addr addr); + void wakeUpBuffer(MessageBuffer* buf, Addr addr); void wakeUpBuffers(Addr addr); void wakeUpAllBuffers(Addr addr); void wakeUpAllBuffers(); diff --git a/src/mem/slicc/ast/WakeupPortStatementAST.py b/src/mem/slicc/ast/WakeupPortStatementAST.py new file mode 100644 index 000000000..cea3d32a1 --- /dev/null +++ b/src/mem/slicc/ast/WakeupPortStatementAST.py @@ -0,0 +1,55 @@ +# Copyright (c) 2021 ARM Limited +# All rights reserved. +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +from slicc.ast.StatementAST import StatementAST + +class WakeupPortStatementAST(StatementAST): + def __init__(self, slicc, in_port, address): + super(StatementAST, self).__init__(slicc) + self.in_port = in_port + self.address = address + + def __repr__(self): + return "[WakeupPortStatementAst: %r]" % self.in_port + + def generate(self, code, return_type): + self.in_port.assertType("InPort") + self.address.assertType("Addr") + + in_port_code = self.in_port.var.code + address_code = self.address.var.code + code(''' + wakeUpBuffer(&($in_port_code), $address_code); + ''') diff --git a/src/mem/slicc/ast/__init__.py b/src/mem/slicc/ast/__init__.py index c41010400..247546fb8 100644 --- a/src/mem/slicc/ast/__init__.py +++ b/src/mem/slicc/ast/__init__.py @@ -1,3 +1,15 @@ +# Copyright (c) 2021 ARM Limited +# All rights reserved. +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# # Copyright (c) 2009 The Hewlett-Packard Development Company # All rights reserved. # @@ -60,6 +72,7 @@ from slicc.ast.PairListAST import * from slicc.ast.PeekStatementAST import * from slicc.ast.ReturnStatementAST import * from slicc.ast.StallAndWaitStatementAST import * +from slicc.ast.WakeupPortStatementAST import * from slicc.ast.StateDeclAST import * from slicc.ast.StatementAST import * from slicc.ast.StatementListAST import * diff --git a/src/mem/slicc/parser.py b/src/mem/slicc/parser.py index 51a68d0b3..73ca835fb 100644 --- a/src/mem/slicc/parser.py +++ b/src/mem/slicc/parser.py @@ -1,4 +1,4 @@ -# Copyright (c) 2020 ARM Limited +# Copyright (c) 2020,2021 ARM Limited # All rights reserved. # # The license below extends only to copyright in the software and shall @@ -118,6 +118,7 @@ class SLICC(Grammar): 'state_declaration' : 'STATE_DECL', 'peek' : 'PEEK', 'stall_and_wait' : 'STALL_AND_WAIT', + 'wakeup_port' : 'WAKEUP_PORT', 'enqueue' : 'ENQUEUE', 'check_allocate' : 'CHECK_ALLOCATE', 'check_next_cycle' : 'CHECK_NEXT_CYCLE', @@ -616,6 +617,10 @@ class SLICC(Grammar): "statement : STALL_AND_WAIT '(' var ',' var ')' SEMI" p[0] = ast.StallAndWaitStatementAST(self, p[3], p[5]) + def p_statement__wakeup_port(self, p): + "statement : WAKEUP_PORT '(' var ',' var ')' SEMI" + p[0] = ast.WakeupPortStatementAST(self, p[3], p[5]) + def p_statement__peek(self, p): "statement : PEEK '(' var ',' type pairs ')' statements" p[0] = ast.PeekStatementAST(self, p[3], p[5], p[6], p[8], "peek") -- 2.30.2