From fc41c3f7e70b6f17803d021a6f03d1043fb01874 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 30 Apr 2021 14:05:01 +0100 Subject: [PATCH] add option to use new mmu_cache_wb ConfigMemoryPortInterface --- src/soc/simple/test/test_runner.py | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/soc/simple/test/test_runner.py b/src/soc/simple/test/test_runner.py index 85a14869..108c9c77 100644 --- a/src/soc/simple/test/test_runner.py +++ b/src/soc/simple/test/test_runner.py @@ -135,8 +135,11 @@ class TestRunner(FHDLTestCase): pc_i = Signal(32) svstate_i = Signal(32) - pspec = TestMemPspec(ldst_ifacetype='test_bare_wb', - imem_ifacetype='test_bare_wb', + ldst_ifacetype = 'mmu_cache_wb' if microwatt_mmu else 'test_bare_wb' + imem_ifacetype = 'test_bare_wb' + + pspec = TestMemPspec(ldst_ifacetype=ldst_ifacetype, + imem_ifacetype=imem_ifacetype, addr_wid=48, mask_wid=8, imem_reg_wid=64, -- 2.30.2