From fc4603f18694aee5e7f6431416ab6ac23ddbd8d2 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 26 Oct 2018 06:46:27 +0100 Subject: [PATCH] add debug printfs --- riscv/sv_insn_redirect.cc | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/riscv/sv_insn_redirect.cc b/riscv/sv_insn_redirect.cc index 3417e69..6e38eaf 100644 --- a/riscv/sv_insn_redirect.cc +++ b/riscv/sv_insn_redirect.cc @@ -105,6 +105,8 @@ void (sv_proc_t::WRITE_REG)(reg_spec_t const& spec, sv_reg_t const& value) offs = *spec.offset; shift = offs % nbytes; offs /= nbytes; + fprintf(stderr, "writereg spec %ld bitwidth %d offs %d shift %d\n", + spec.reg, bitwidth, offs, shift); reg += offs; } if (xlen != bitwidth) @@ -114,7 +116,7 @@ void (sv_proc_t::WRITE_REG)(reg_spec_t const& spec, sv_reg_t const& value) wval = wval << (shift*bitwidth); // gets element within the reg-block uint64_t ndata = data & (uint64_t)(~mask); // masks off the right bits wval |= ndata; - fprintf(stderr, "writereg %lx bitwidth %d offs %d shift %d %lx " \ + fprintf(stderr, "writereg %ld bitwidth %d offs %d shift %d %lx " \ " %lx %lx %lx\n", spec.reg, bitwidth, offs, shift, data, ndata, mask, wval); @@ -343,6 +345,8 @@ sv_reg_t sv_proc_t::rv_add(sv_reg_t const & lhs, sv_reg_t const & rhs) { uint8_t bitwidth = _insn->src_bitwidth; if (bitwidth == xlen) { + //fprintf(stderr, "add result %lx %lx %lx\n", + // (uint64_t)lhs, (uint64_t)rhs, (uint64_t)(lhs + rhs)); return lhs + rhs; } uint64_t vlhs = 0; @@ -364,6 +368,7 @@ sv_reg_t sv_proc_t::rv_add(sv_reg_t const & lhs, sv_reg_t const & rhs) result = zext_bwid(result, bitwidth); } uint8_t reswidth = maxelwidth(lhs.get_elwidth(), rhs.get_elwidth()); + //fprintf(stderr, "add result %ld\n", result); return sv_reg_t(result, xlen, reswidth); // XXX TODO: bitwidth } -- 2.30.2