From fc6eb109d9bda4a584a3923772c8348e48859ebb Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 20 Jun 2022 17:38:35 +0100 Subject: [PATCH] minor clarify --- svp64-primer/summary.tex | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/svp64-primer/summary.tex b/svp64-primer/summary.tex index e7bfb5d0c..1e0264b83 100644 --- a/svp64-primer/summary.tex +++ b/svp64-primer/summary.tex @@ -76,8 +76,8 @@ performance, CPU architects typically increase the width of registers (to 128-, 256-, 512-bit etc) for more partitions.\par Additionally, binary compatibility is an important feature, and thus each doubling of SIMD registers also expands the instruction set. The number of -instructions quickly balloons and this can be seen in popular \ac{ISA}, -for example IA-32 expanding from 80 to about 1400 instructions since +instructions quickly balloons and this can be seen in for example +IA-32 expanding from 80 to about 1400 instructions since 1978\cite{SIMD_HARM}.\par \subsection{Vector Architectures} -- 2.30.2