From fc7eed0dfaffea6f0af24d924a1d55eb7e72553a Mon Sep 17 00:00:00 2001 From: lkcl Date: Sun, 23 Apr 2023 12:03:58 +0100 Subject: [PATCH] --- openpower/sv/svp64.mdwn | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn index de08ccdba..55e537018 100644 --- a/openpower/sv/svp64.mdwn +++ b/openpower/sv/svp64.mdwn @@ -814,6 +814,14 @@ The SUBVL encoding value may be thought of as an inclusive range of a sub-vector. SUBVL=2 represents a vec2, its encoding is 0b01, therefore this may be considered to be elements 0b00 to 0b01 inclusive. +Effectively, SUBVL is like a SIMD multiplier: instead of just 1 +element operation issued, SUBVL element operations are issued (as an inner loop). +The key difference between VL looping and SUBVL looping +is that predication bits are applied per +**group**, rather than by individual element. + +Directly related to `subvl` is the `pack` and `unpack` Mode bits of `SVSTATE`. + ## MASK/MASK_SRC & MASKMODE Encoding One bit (`MASKMODE`) indicates the mode: CR or Int predication. The two -- 2.30.2