From fcc58e0d11571a5ed83af12d9418ba87712c5d18 Mon Sep 17 00:00:00 2001
From: Shriya Sharma <shriya@redsemiconductor.com>
Date: Thu, 19 Oct 2023 11:01:27 +0100
Subject: [PATCH]  Added lbzsx and lbzsux instructions

---
 openpower/isa/fixedloadshift.mdwn | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/openpower/isa/fixedloadshift.mdwn b/openpower/isa/fixedloadshift.mdwn
index 75be291a..bc488ad0 100644
--- a/openpower/isa/fixedloadshift.mdwn
+++ b/openpower/isa/fixedloadshift.mdwn
@@ -26,31 +26,31 @@
 <!-- halfword, word, or doubleword) addressed by EA is loaded into RT. -->
 
 
-# Load Byte and Zero Indexed
+# Load Byte and Zero Shifted Indexed 
 
 X-Form
 
-* lbzx RT,RA,RB
+* lbzsx RT,RA,RB,sh
 
 Pseudo-code:
 
     b <- (RA|0)
-    EA <- b + (RB)
+    EA <- b + (RB) << (sh+1)
     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
 
 Special Registers Altered:
 
     None
 
-# Load Byte and Zero with Update Indexed
+# Load Byte and Zero Shifted with Update Indexed
 
 X-Form
 
-* lbzux RT,RA,RB
+* lbzsux RT,RA,RB,sh
 
 Pseudo-code:
 
-    EA <- (RA) + (RB)
+    EA <- (RA) + (RB) << (sh+1)
     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
     RA <- EA
 
-- 
2.30.2