From fcc9fe1e6a3ce2e0af318fc3988456673dfa0239 Mon Sep 17 00:00:00 2001 From: "H.J. Lu" Date: Mon, 12 May 2008 20:29:37 +0000 Subject: [PATCH] sse.md (*sse_concatv4sf): Renamed to ... gcc/ 2008-05-12 H.J. Lu * config/i386/sse.md (*sse_concatv4sf): Renamed to ... (*vec_concatv4sf_sse): This. (*sse2_concatv2si): Renamed to ... (*vec_concatv2si_sse2): This. (*sse1_concatv2si): Renamed to ... (*vec_concatv2si_sse): This. (*vec_concatv2di_rex): Renamed to ... (*vec_concatv2di_rex64): This. (*vec_concatv2si_sse4_1): New. (*vec_concatv2di_rex64_sse4_1): Likewise. gcc/testsuite 2008-05-12 H.J. Lu * gcc.target/i386/sse2-set-epi32-1.c: New. * gcc.target/i386/sse2-set-epi64x-1.c: Likewise. * gcc.target/i386/sse4_1-set-epi32-1.c: Likewise. * gcc.target/i386/sse4_1-set-epi64x-1.c: Likewise. From-SVN: r135229 --- gcc/ChangeLog | 13 ++++++ gcc/config/i386/sse.md | 34 ++++++++++++--- gcc/testsuite/ChangeLog | 7 ++++ .../gcc.target/i386/sse2-set-epi32-1.c | 41 ++++++++++++++++++ .../gcc.target/i386/sse2-set-epi64x-1.c | 41 ++++++++++++++++++ .../gcc.target/i386/sse4_1-set-epi32-1.c | 42 +++++++++++++++++++ .../gcc.target/i386/sse4_1-set-epi64x-1.c | 42 +++++++++++++++++++ 7 files changed, 215 insertions(+), 5 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/sse2-set-epi32-1.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-set-epi64x-1.c create mode 100644 gcc/testsuite/gcc.target/i386/sse4_1-set-epi32-1.c create mode 100644 gcc/testsuite/gcc.target/i386/sse4_1-set-epi64x-1.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 2d309c04363..bcf6c64b6a3 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,16 @@ +2008-05-12 H.J. Lu + + * config/i386/sse.md (*sse_concatv4sf): Renamed to ... + (*vec_concatv4sf_sse): This. + (*sse2_concatv2si): Renamed to ... + (*vec_concatv2si_sse2): This. + (*sse1_concatv2si): Renamed to ... + (*vec_concatv2si_sse): This. + (*vec_concatv2di_rex): Renamed to ... + (*vec_concatv2di_rex64): This. + (*vec_concatv2si_sse4_1): New. + (*vec_concatv2di_rex64_sse4_1): Likewise. + 2008-05-12 Uros Bizjak PR rtl-optimization/36111 diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index d31aceb5d1b..983ffcf6c46 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -2253,7 +2253,7 @@ ;; ??? In theory we can match memory for the MMX alternative, but allowing ;; nonimmediate_operand for operand 2 and *not* allowing memory for the SSE ;; alternatives pretty much forces the MMX alternative to be chosen. -(define_insn "*sse_concatv2sf" +(define_insn "*vec_concatv2sf_sse" [(set (match_operand:V2SF 0 "register_operand" "=x,x,*y,*y") (vec_concat:V2SF (match_operand:SF 1 "nonimmediate_operand" " 0,m, 0, m") @@ -2267,7 +2267,7 @@ [(set_attr "type" "sselog,ssemov,mmxcvt,mmxmov") (set_attr "mode" "V4SF,SF,DI,DI")]) -(define_insn "*sse_concatv4sf" +(define_insn "*vec_concatv4sf_sse" [(set (match_operand:V4SF 0 "register_operand" "=x,x") (vec_concat:V4SF (match_operand:V2SF 1 "register_operand" " 0,0") @@ -4726,10 +4726,22 @@ [(set_attr "type" "sselog1,ssemov") (set_attr "mode" "TI,V4SF")]) +(define_insn "*vec_concatv2si_sse4_1" + [(set (match_operand:V2SI 0 "register_operand" "=x,x") + (vec_concat:V2SI + (match_operand:SI 1 "nonimmediate_operand" "0,rm") + (match_operand:SI 2 "nonimmediate_operand" "rm,0")))] + "TARGET_SSE4_1" + "@ + pinsrd\t{$0x1, %2, %0|%0, %2, 0x1} + pinsrd\t{$0x0, %2, %0|%0, %2, 0x0}" + [(set_attr "type" "sselog") + (set_attr "mode" "TI")]) + ;; ??? In theory we can match memory for the MMX alternative, but allowing ;; nonimmediate_operand for operand 2 and *not* allowing memory for the SSE ;; alternatives pretty much forces the MMX alternative to be chosen. -(define_insn "*sse2_concatv2si" +(define_insn "*vec_concatv2si_sse2" [(set (match_operand:V2SI 0 "register_operand" "=Y2, Y2,*y,*y") (vec_concat:V2SI (match_operand:SI 1 "nonimmediate_operand" " 0 ,rm , 0,rm") @@ -4743,7 +4755,7 @@ [(set_attr "type" "sselog,ssemov,mmxcvt,mmxmov") (set_attr "mode" "TI,TI,DI,DI")]) -(define_insn "*sse1_concatv2si" +(define_insn "*vec_concatv2si_sse" [(set (match_operand:V2SI 0 "register_operand" "=x,x,*y,*y") (vec_concat:V2SI (match_operand:SI 1 "nonimmediate_operand" " 0,m, 0,*rm") @@ -4770,6 +4782,18 @@ [(set_attr "type" "sselog,ssemov,ssemov") (set_attr "mode" "TI,V4SF,V2SF")]) +(define_insn "*vec_concatv2di_rex64_sse4_1" + [(set (match_operand:V2DI 0 "register_operand" "=x,x") + (vec_concat:V2DI + (match_operand:DI 1 "nonimmediate_operand" "0,rm") + (match_operand:DI 2 "nonimmediate_operand" "rm,0")))] + "TARGET_64BIT && TARGET_SSE4_1" + "@ + pinsrq\t{$0x1, %2, %0|%0, %2, 0x1} + pinsrq\t{$0x0, %2, %0|%0, %2, 0x0}" + [(set_attr "type" "sselog") + (set_attr "mode" "TI")]) + (define_insn "vec_concatv2di" [(set (match_operand:V2DI 0 "register_operand" "=Y2,?Y2,Y2,x,x,x") (vec_concat:V2DI @@ -4786,7 +4810,7 @@ [(set_attr "type" "ssemov,ssemov,sselog,ssemov,ssemov,ssemov") (set_attr "mode" "TI,TI,TI,V4SF,V2SF,V2SF")]) -(define_insn "*vec_concatv2di_rex" +(define_insn "*vec_concatv2di_rex64" [(set (match_operand:V2DI 0 "register_operand" "=Y2,Yi,!Y2,Y2,x,x,x") (vec_concat:V2DI (match_operand:DI 1 "nonimmediate_operand" " m,r ,*y ,0 ,0,0,m") diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index e2624e44e41..755d6832a89 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,10 @@ +2008-05-12 H.J. Lu + + * gcc.target/i386/sse2-set-epi32-1.c: New. + * gcc.target/i386/sse2-set-epi64x-1.c: Likewise. + * gcc.target/i386/sse4_1-set-epi32-1.c: Likewise. + * gcc.target/i386/sse4_1-set-epi64x-1.c: Likewise. + 2008-05-12 Uros Bizjak PR rtl-optimization/36111 diff --git a/gcc/testsuite/gcc.target/i386/sse2-set-epi32-1.c b/gcc/testsuite/gcc.target/i386/sse2-set-epi32-1.c new file mode 100644 index 00000000000..f4dac40fc99 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-set-epi32-1.c @@ -0,0 +1,41 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ + +#include "sse2-check.h" + +#ifdef DEBUG +#include +#endif + +#include + +static void +__attribute__((noinline)) +test (unsigned int *v) +{ + union + { + __m128i x; + unsigned int i[4]; + } u; + unsigned int i; + + u.x = _mm_set_epi32 (v[3], v[2], v[1], v[0]); + + for (i = 0; i < sizeof (v) / sizeof (v[0]); i++) + if (v[i] != u.i[i]) + { +#ifdef DEBUG + printf ("%i: 0x%x != 0x%x\n", i, v[i], u.i[i]); +#endif + abort (); + } +} + +static void +sse2_test (void) +{ + unsigned int v[4] + = { 0x7B5B5465, 0x73745665, 0x63746F72, 0x5D53475D }; + test (v); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-set-epi64x-1.c b/gcc/testsuite/gcc.target/i386/sse2-set-epi64x-1.c new file mode 100644 index 00000000000..67510b59c7e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-set-epi64x-1.c @@ -0,0 +1,41 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ + +#include "sse2-check.h" + +#ifdef DEBUG +#include +#endif + +#include + +static void +__attribute__((noinline)) +test (unsigned long long *v) +{ + union + { + __m128i x; + unsigned long long i[2]; + } u; + unsigned int i; + + u.x = _mm_set_epi64x (v[1], v[0]); + + for (i = 0; i < sizeof (v) / sizeof (v[0]); i++) + if (v[i] != u.i[i]) + { +#ifdef DEBUG + printf ("%i: 0x%llx != 0x%llx\n", i, v[i], u.i[i]); +#endif + abort (); + } +} + +static void +sse2_test (void) +{ + unsigned long long v[2] + = { 0x7B5B546573745665LL, 0x63746F725D53475DLL }; + test (v); +} diff --git a/gcc/testsuite/gcc.target/i386/sse4_1-set-epi32-1.c b/gcc/testsuite/gcc.target/i386/sse4_1-set-epi32-1.c new file mode 100644 index 00000000000..989e4f7086f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse4_1-set-epi32-1.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ + +#include "sse4_1-check.h" + +#ifdef DEBUG +#include +#endif + +#include + +static void +__attribute__((noinline)) +test (unsigned int *v) +{ + union + { + __m128i x; + unsigned int i[4]; + } u; + unsigned int i; + + u.x = _mm_set_epi32 (v[3], v[2], v[1], v[0]); + + for (i = 0; i < sizeof (v) / sizeof (v[0]); i++) + if (v[i] != u.i[i]) + { +#ifdef DEBUG + printf ("%i: 0x%x != 0x%x\n", i, v[i], u.i[i]); +#endif + abort (); + } +} + +static void +sse4_1_test (void) +{ + unsigned int v[4] + = { 0x7B5B5465, 0x73745665, 0x63746F72, 0x5D53475D }; + test (v); +} diff --git a/gcc/testsuite/gcc.target/i386/sse4_1-set-epi64x-1.c b/gcc/testsuite/gcc.target/i386/sse4_1-set-epi64x-1.c new file mode 100644 index 00000000000..8679f52860f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse4_1-set-epi64x-1.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ + +#include "sse4_1-check.h" + +#ifdef DEBUG +#include +#endif + +#include + +static void +__attribute__((noinline)) +test (unsigned long long *v) +{ + union + { + __m128i x; + unsigned long long i[2]; + } u; + unsigned int i; + + u.x = _mm_set_epi64x (v[1], v[0]); + + for (i = 0; i < sizeof (v) / sizeof (v[0]); i++) + if (v[i] != u.i[i]) + { +#ifdef DEBUG + printf ("%i: 0x%llx != 0x%llx\n", i, v[i], u.i[i]); +#endif + abort (); + } +} + +static void +sse4_1_test (void) +{ + unsigned long long v[2] + = { 0x7B5B546573745665LL, 0x63746F725D53475DLL }; + test (v); +} -- 2.30.2