From fccfb410ed751ce5fe5570a7d174834b26bcbb7f Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 30 Aug 2022 13:22:50 +0100 Subject: [PATCH] correct the bitmanip pseudocode to remove spaces from instruction declarations ternlogi RT,RA,RB,TLI not ternlog RT, RA, RB, TLI --- openpower/isa/bitmanip.mdwn | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/openpower/isa/bitmanip.mdwn b/openpower/isa/bitmanip.mdwn index d1521a76..d5b9dddb 100644 --- a/openpower/isa/bitmanip.mdwn +++ b/openpower/isa/bitmanip.mdwn @@ -5,8 +5,8 @@ TLI-Form -* ternlogi RT, RA, RB, TLI -* ternlogi. RT, RA, RB, TLI +* ternlogi RT,RA,RB,TLI +* ternlogi. RT,RA,RB,TLI Pseudo-code: @@ -24,8 +24,8 @@ Special Registers Altered: X-Form -* grev RT, RA, RB (Rc=0) -* grev. RT, RA, RB (Rc=1) +* grev RT,RA,RB (Rc=0) +* grev. RT,RA,RB (Rc=1) Pseudo-code: @@ -44,8 +44,8 @@ Special Registers Altered: XB-Form -* grevi RT, RA, XBI (Rc=0) -* grevi. RT, RA, XBI (Rc=1) +* grevi RT,RA,XBI (Rc=0) +* grevi. RT,RA,XBI (Rc=1) Pseudo-code: @@ -63,8 +63,8 @@ Special Registers Altered: X-Form -* grevw RT, RA, RB (Rc=0) -* grevw. RT, RA, RB (Rc=1) +* grevw RT,RA,RB (Rc=0) +* grevw. RT,RA,RB (Rc=1) Pseudo-code: @@ -84,8 +84,8 @@ Special Registers Altered: X-Form -* grevwi RT, RA, SH (Rc=0) -* grevwi. RT, RA, SH (Rc=1) +* grevwi RT,RA,SH (Rc=0) +* grevwi. RT,RA,SH (Rc=1) Pseudo-code: -- 2.30.2