From fcd1ee07d35e970766622ea09e79a9b80c632cf9 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Sat, 26 Mar 2011 06:02:41 +0000 Subject: [PATCH] sim: bfin: add missing VS set with add/sub insns The 16bit add/sub insns missed setting the VS bit in ASTAT whenever the V bit was also set. Signed-off-by: Robin Getz Signed-off-by: Mike Frysinger --- sim/bfin/ChangeLog | 4 ++++ sim/bfin/bfin-sim.c | 3 +++ 2 files changed, 7 insertions(+) diff --git a/sim/bfin/ChangeLog b/sim/bfin/ChangeLog index eacab65bbf7..008edf0f9d3 100644 --- a/sim/bfin/ChangeLog +++ b/sim/bfin/ChangeLog @@ -1,3 +1,7 @@ +2011-03-26 Robin Getz + + * bfin-sim.c (decode_dsp32alu_0): Set VS when V is set. + 2011-03-24 Mike Frysinger * dv-bfin_gpio.c (bfin_gpio_port_event): Call HW_TRACE at every diff --git a/sim/bfin/bfin-sim.c b/sim/bfin/bfin-sim.c index 467d7423070..7e747ff1e34 100644 --- a/sim/bfin/bfin-sim.c +++ b/sim/bfin/bfin-sim.c @@ -4122,6 +4122,9 @@ decode_dsp32alu_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1) SET_ASTATREG (ac0, ac0_i); SET_ASTATREG (v, v_i); + if (v_i) + SET_ASTATREG (vs, v_i); + if (HL) SET_DREG_H (dst0, val << 16); else -- 2.30.2