From fcfaf91e18a57b0aa1dd8abcf183c07365e03bde Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 22 Mar 2022 16:59:31 +0000
Subject: [PATCH] adding hyperram for arty a7 and also adding a workaround for
 some stupid issues

---
 coldboot/coldboot.c      |  2 +-
 src/arty_a7_ls2.py       |  3 +++
 src/ls2.py               | 46 ++++++++++++++++++++++++++++------------
 src/versa_ecp5_85_ls2.py |  3 +++
 4 files changed, 40 insertions(+), 14 deletions(-)
 create mode 100644 src/arty_a7_ls2.py
 create mode 100644 src/versa_ecp5_85_ls2.py

diff --git a/coldboot/coldboot.c b/coldboot/coldboot.c
index 2496670..8b746d2 100644
--- a/coldboot/coldboot.c
+++ b/coldboot/coldboot.c
@@ -67,7 +67,7 @@ int main(void) {
 	//puts("Firmware launched...\n");
 
 	puts("fw..");
-#if 0
+#if 1
 	volatile uint32_t *hyperram = 0xa0000000;
     // quick write/read
     writel(0xDEAF0000, (unsigned long)&(hyperram[0]));
diff --git a/src/arty_a7_ls2.py b/src/arty_a7_ls2.py
new file mode 100644
index 0000000..180e845
--- /dev/null
+++ b/src/arty_a7_ls2.py
@@ -0,0 +1,3 @@
+from ls2 import build_platform
+
+build_platform("arty_a7", "coldboot/coldboot.bin")
diff --git a/src/ls2.py b/src/ls2.py
index 855ddd3..269fdb5 100644
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -546,13 +546,9 @@ class DDR3SoC(SoC, Elaboratable):
         ports += [ClockSignal(), ResetSignal()]
         return ports
 
-if __name__ == "__main__":
+def build_platform(fpga, firmware):
 
-    # create a platform selected from the toolchain. defaults to VERSA_ECP5
-    # only VERSA_ECP5 will work for now because of the DDR3 module
-    fpga = "versa_ecp5"
-    if len(sys.argv) >= 2:
-        fpga = sys.argv[1]
+    # create a platform selected from the toolchain. 
     platform_kls =  {'versa_ecp5': VersaECP5Platform,
                      'versa_ecp5_85': VersaECP5Platform85,
                      'ulx3s': ULX3S_85F_Platform,
@@ -591,13 +587,13 @@ if __name__ == "__main__":
     if fpga == 'arty_a7':
         clk_freq = 12e6
 
-    # select a firmware file
-    firmware = None
+    # select a firmware address
     fw_addr = None
-    if len(sys.argv) >= 3:
-        firmware = sys.argv[2]
+    if firmware is not None:
         fw_addr = 0x0000_0000
 
+    print ("fpga", fpga, "firmware", firmware)
+
     # get UART resource pins
     if platform is not None:
         uart_pins = platform.request("uart", 0)
@@ -631,15 +627,28 @@ if __name__ == "__main__":
 
     # Get HyperRAM pins
     hyperram_pins = None
-    if platform is not None and fpga in ['versa_ecp5', 'versa_ecp5_85']:
+    if platform is None or platform in ['isim']:
+        hyperram_pins = HyperRAMPads()
+    # Digilent Arty A7-100t
+    elif platform is not None and fpga in ['arty_a7']:
+        hyperram_ios = HyperRAMResource(0, cs_n="B11",
+                                        dq="D4 D3 F4 F3 G2 H2 D2 E2",
+                                        rwds="U13", rst_n="T13", ck_p="V10"
+                                        # ck_n="D12" - for later (DDR)
+                                        )
+                                        #attrs=Attrs(IO_TYPE="LVCMOS33"))
+        platform.add_resources(hyperram_ios)
+        hyperram_pins = platform.request("hyperram")
+        print ("arty a7 hyperram", hyperram_ios)
+    # VERSA ECP5
+    elif platform is not None and fpga in ['versa_ecp5', 'versa_ecp5_85']:
         hyperram_ios = HyperRAMResource(0, cs_n="B13",
                                         dq="E14 C10 B10 E12 D12 A9 D11 D14",
                                         rwds="C14", rst_n="E13", ck_p="D13",
                                         attrs=Attrs(IO_TYPE="LVCMOS33"))
         platform.add_resources(hyperram_ios)
         hyperram_pins = platform.request("hyperram")
-    else:
-        hyperram_pins = HyperRAMPads()
+        print ("versa ecp5 hyperram", hyperram_ios)
 
     # set up the SOC
     soc = DDR3SoC(fpga=fpga, dram_cls=dram_cls,
@@ -679,3 +688,14 @@ if __name__ == "__main__":
         with open("ls2.v", "w") as f:
             f.write(vl)
 
+
+# urrr this gets exec()d by the build process without arguments
+# which screws up.  use the arty_a7_ls2.py etc. with no arguments
+if __name__ == '__main__':
+    fpga = None
+    firmware = None
+    if len(sys.argv) >= 2:
+        fpga = sys.argv[1]
+    if len(sys.argv) >= 3:
+        firmware = sys.argv[2]
+    build_platform(fpga, firmware)
diff --git a/src/versa_ecp5_85_ls2.py b/src/versa_ecp5_85_ls2.py
new file mode 100644
index 0000000..e5780b0
--- /dev/null
+++ b/src/versa_ecp5_85_ls2.py
@@ -0,0 +1,3 @@
+from ls2 import build_platform
+
+build_platform("versa_ecp5_85", "coldboot/coldboot.bin")
-- 
2.30.2