From fcfe66696d70a16981c8b6435ef7341b29b220ef Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 9 Jul 2018 03:04:30 +0100 Subject: [PATCH] add test module which is dynamically created --- src/myhdl/pins.py | 27 ++++++++++++++++----------- 1 file changed, 16 insertions(+), 11 deletions(-) diff --git a/src/myhdl/pins.py b/src/myhdl/pins.py index bc3c026..832b3f8 100644 --- a/src/myhdl/pins.py +++ b/src/myhdl/pins.py @@ -50,10 +50,11 @@ def Test(*args): def create_test(): x = """\ -def getfn({0}): - def test({0}): - args = ({0}) - return test2(*args) +from myhdl import block +@block +def test(testfn, {0}): + args = ({0}) + return testfn(*args) return test """ args = ['clk', 'muxes', 'pins', 'fns'] @@ -61,12 +62,13 @@ def getfn({0}): x = x.format(args) print x print repr(x) - y = {'test2': test2, 'block': block} + with open("testmod.py", "w") as f: + f.write(x) + x = "from testmod import test" code = compile(x, '', 'exec') + y = {} exec code in y - x = y["getfn"] - #print inspect.getsourcelines(proxy) - #print inspect.getsourcelines(x) + x = y["test"] def fn(*args): return block(x) @@ -79,6 +81,7 @@ def proxy(func): return wrapper +@block def test2(clk, muxes, pins, fns): muxinst = [] @@ -120,7 +123,7 @@ def mux_tb(): fns.append(IO("inout", "fnname%d" % i)) clk = Signal(bool(0)) - mux_inst = Test(clk, muxes, pins, fns) + mux_inst = test(test2, clk, muxes, pins, fns) @instance def clk_signal(): @@ -166,7 +169,9 @@ def test_mux(): fns.append(IO("inout", "fnname%d" % i)) clk = Signal(bool(0)) - mux_inst = Test(clk, muxes, pins, fns) + mux_inst = test(test2, clk, muxes, pins, fns) + mux_inst.convert(hdl="Verilog", initial_values=True) + #mux_inst = Test(clk, muxes, pins, fns) #toVerilog(mux_inst, clk, muxes, pins, fns) #deco = Deco() #b = _Block(mux_inst, deco, "test", "test.py", 1, clk, muxes, pins, fns) @@ -182,7 +187,7 @@ def test_mux(): tb.config_sim(trace=True) tb.run_sim(66 * period) # run for 15 clock cycle -#test = create_test() +test = create_test() if __name__ == '__main__': -- 2.30.2