From fd0c07143003bfa3ce6a0ab5c614e12a4469bb1a Mon Sep 17 00:00:00 2001 From: Shriya Sharma Date: Tue, 17 Oct 2023 13:55:51 +0100 Subject: [PATCH] added spaces for the pifixedload.mdwm file --- openpower/isa/pifixedload.mdwn | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/openpower/isa/pifixedload.mdwn b/openpower/isa/pifixedload.mdwn index ab2477bc..fec60a27 100644 --- a/openpower/isa/pifixedload.mdwn +++ b/openpower/isa/pifixedload.mdwn @@ -22,8 +22,8 @@ Pseudo-code: Description: - Let the effective address (EA) be register RA. The - byte in storage addressed by EA is loaded into RT[56:63]. + Let the effective address (EA) be register RA. + The byte in storage addressed by EA is loaded into RT[56:63]. RT[0:55] are set to 0. The sum (RA) + D is placed into register RA. @@ -49,8 +49,8 @@ Pseudo-code: Description: Let the effective address (EA) be register RA. - The byte in storage addressed by EA is loaded into - RT[56:63]. RT[0:55] are set to 0. + The byte in storage addressed by EA is loaded into RT[56:63]. + RT[0:55] are set to 0. The sum (RA) + (RB) is placed into register RA. @@ -74,9 +74,9 @@ Pseudo-code: Description: - Let the effective address (EA) be register RA. The - halfword in storage addressed by EA is loaded into - RT[48:63]. RT[0:47] are set to 0. + Let the effective address (EA) be register RA. + The halfword in storage addressed by EA is loaded into RT[48:63]. + RT[0:47] are set to 0. The sum (RA) + D is placed into register RA. @@ -101,8 +101,8 @@ Pseudo-code: Description: Let the effective address (EA) be register RA. - The halfword in storage addressed by EA is loaded into - RT[48:63]. RT[0:47] are set to 0. + The halfword in storage addressed by EA is loaded into RT[48:63]. + RT[0:47] are set to 0. The sum (RA) + (RB) is placed into register RA. -- 2.30.2