From fd2f8d4bb4b1c92b6b2b2aa06d38d7ee4ac6290c Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Sat, 21 Mar 2015 17:04:58 +0100
Subject: [PATCH] sdram: define MT46V32M16 and use it on m1/mixxeo

---
 misoclib/mem/sdram/module.py | 16 ++++++++++++++++
 targets/mlabs_video.py       | 17 +++--------------
 2 files changed, 19 insertions(+), 14 deletions(-)

diff --git a/misoclib/mem/sdram/module.py b/misoclib/mem/sdram/module.py
index 10a69eec..773b6450 100644
--- a/misoclib/mem/sdram/module.py
+++ b/misoclib/mem/sdram/module.py
@@ -62,6 +62,22 @@ class MT48LC4M16(SDRAMModule):
 		SDRAMModule.__init__(self, clk_freq, self.geom_settings, self.timing_settings)
 
 # DDR
+class MT46V32M16(SDRAMModule):
+	geom_settings = {
+		"nbanks":	4,
+		"nrows":	8192,
+		"ncols":	1024
+	}
+	timing_settings = {
+		"tRP":		15,
+		"tRCD":		15,
+		"tWR":		15,
+		"tWTR":		2,
+		"tREFI":	7800,
+		"tRFC":		70
+	}
+	def __init__(self, clk_freq):
+		SDRAMModule.__init__(self, clk_freq, self.geom_settings, self.timing_settings)
 
 # LPDDR
 
diff --git a/targets/mlabs_video.py b/targets/mlabs_video.py
index 54943497..ddd24380 100644
--- a/targets/mlabs_video.py
+++ b/targets/mlabs_video.py
@@ -6,6 +6,7 @@ from mibuild.generic_platform import ConstraintError
 
 from misoclib.others import mxcrg
 from misoclib.mem import sdram
+from misoclib.mem.sdram.module import MT46V32M16
 from misoclib.mem.sdram.phy import s6ddrphy
 from misoclib.mem.flash import norflash16
 from misoclib.cpu.peripherals import gpio
@@ -41,19 +42,7 @@ class BaseSoC(SDRAMSoC):
 		self.submodules.crg = mxcrg.MXCRG(_MXClockPads(platform), self.clk_freq)
 
 		if not self.with_main_ram:
-			sdram_geom_settings = sdram.GeomSettings(
-				bank_a=2,
-				row_a=13,
-				col_a=10
-			)
-			sdram_timing_settings = sdram.TimingSettings(
-				tRP=self.ns(15),
-				tRCD=self.ns(15),
-				tWR=self.ns(15),
-				tWTR=2,
-				tREFI=self.ns(7800, False),
-				tRFC=self.ns(70),
-			)
+			sdram_module = MT46V32M16(self.clk_freq)
 			sdram_controller_settings =  sdram.ControllerSettings(
 				req_queue_size=8,
 				read_time=32,
@@ -61,7 +50,7 @@ class BaseSoC(SDRAMSoC):
 			)
 			self.submodules.ddrphy = s6ddrphy.S6DDRPHY(platform.request("ddram"), memtype="DDR",
 				rd_bitslip=0, wr_bitslip=3, dqs_ddr_alignment="C1")
-			self.register_sdram_phy(self.ddrphy, sdram_geom_settings, sdram_timing_settings,
+			self.register_sdram_phy(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings,
 				sdram_controller_settings)
 
 
-- 
2.30.2