From fd31ffb01423cdf0e775ee8e8ff5b16c86b95577 Mon Sep 17 00:00:00 2001 From: whitequark Date: Sun, 8 Sep 2019 12:24:18 +0000 Subject: [PATCH] hdl.dsl: add Default(), an alias for Case() with no arguments. Fixes #197. --- nmigen/hdl/dsl.py | 3 +++ nmigen/test/test_hdl_dsl.py | 19 ++++++++++++++++++- 2 files changed, 21 insertions(+), 1 deletion(-) diff --git a/nmigen/hdl/dsl.py b/nmigen/hdl/dsl.py index 7f85f2d..5b7aae9 100644 --- a/nmigen/hdl/dsl.py +++ b/nmigen/hdl/dsl.py @@ -289,6 +289,9 @@ class Module(_ModuleBuilderRoot, Elaboratable): self._ctrl_context = "Switch" self._statements = _outer_case + def Default(self): + return self.Case() + @contextmanager def FSM(self, reset=None, domain="sync", name="fsm"): self._check_context("FSM", context=None) diff --git a/nmigen/test/test_hdl_dsl.py b/nmigen/test/test_hdl_dsl.py index 02433d8..5a57988 100644 --- a/nmigen/test/test_hdl_dsl.py +++ b/nmigen/test/test_hdl_dsl.py @@ -307,7 +307,7 @@ class DSLTestCase(FHDLTestCase): ) """) - def test_Switch_default(self): + def test_Switch_default_Case(self): m = Module() with m.Switch(self.w1): with m.Case(3): @@ -324,6 +324,23 @@ class DSLTestCase(FHDLTestCase): ) """) + def test_Switch_default_Default(self): + m = Module() + with m.Switch(self.w1): + with m.Case(3): + m.d.comb += self.c1.eq(1) + with m.Default(): + m.d.comb += self.c2.eq(1) + m._flush() + self.assertRepr(m._statements, """ + ( + (switch (sig w1) + (case 0011 (eq (sig c1) (const 1'd1))) + (default (eq (sig c2) (const 1'd1))) + ) + ) + """) + def test_Switch_const_test(self): m = Module() with m.Switch(1): -- 2.30.2