From fd342dc21fc4a07654b73f38619752b37824cd8f Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 4 Mar 2019 09:12:41 +0000
Subject: [PATCH] comments and whitespace cleanup

---
 TLB/src/CacheWalker.py | 2 +-
 TLB/src/CamEntry.py    | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/TLB/src/CacheWalker.py b/TLB/src/CacheWalker.py
index b075828e..d0d33980 100644
--- a/TLB/src/CacheWalker.py
+++ b/TLB/src/CacheWalker.py
@@ -23,7 +23,7 @@ class CacheWalker():
         self.assoc = assoc # Assciativity of the cache
 
         self.read_port = mem.read_port
-        self.write_port = mem.write_port 
+        self.write_port = mem.write_port
 
         if (mem_size % assoc != 0):
             print("Cache Walker: Memory cannot be distributed between sets")
diff --git a/TLB/src/CamEntry.py b/TLB/src/CamEntry.py
index 8be65622..726fb126 100644
--- a/TLB/src/CamEntry.py
+++ b/TLB/src/CamEntry.py
@@ -25,7 +25,7 @@ class CamEntry:
         # Output
         self.match = Signal(1) # Result of the internal/input key comparison
         self.data = Signal(data_size)
- 
+
     def elaborate(self, platform=None):
         m = Module()
         with m.Switch(self.command):
-- 
2.30.2