From fd3d3a04f30f71722aa96346cb785e5c3e780014 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sun, 28 May 2023 10:30:18 +0100 Subject: [PATCH] --- openpower/sv/svp64.mdwn | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn index 5eb1382e9..434d87bdf 100644 --- a/openpower/sv/svp64.mdwn +++ b/openpower/sv/svp64.mdwn @@ -82,13 +82,19 @@ Branch-Conditional behaviour into a much more advanced variant that is highly suited to High-Performance Computation (HPC), Supercomputing, and parallel GPU Workloads. -*Architectural Resource Allocation note: it is prohibited to accept RFCs +*Architectural Resource Allocation note: at present it is possible to perform +partial parallel decode of the SVP64 24-bit Encoding at the same time +as decoding of the Suffix. Multi-Issue Implementations may even +Decode multiple 32-bit words in parallel and follow up with a second +cycle of joining Prefix and Suffix "after-the-fact". +Mixing and overlaying 64-bit Opcode Encodings into the +{SVP64 24-bit Prefix}{Defined word-instruction} space creates +a hard dependency that catastrophically damages Multi-Issue Decoding. +Therefore it has to be prohibited to accept RFCs which fundamentally violate this hard requirement. Under no circumstances must the Suffix space have an alternate instruction encoding allocated -within SVP64 that is entirely different from the non-prefixed Defined -Word. Hardware Implementors critically rely on this inviolate guarantee -to implement High-Performance Multi-Issue micro-architectures that can -sustain 100% throughput* + that is entirely different from the non-prefixed Defined +Word.* Subset implementations in hardware are permitted, as long as certain rules are followed, allowing for full soft-emulation including future -- 2.30.2