From fd43603414a9b7bdbac5a822af144dcd559733eb Mon Sep 17 00:00:00 2001 From: Christophe Lyon Date: Wed, 2 Dec 2020 12:20:02 +0000 Subject: [PATCH] arm: Auto-vectorization for MVE: vmvn This patch enables MVE vmvnq instructions for auto-vectorization. MVE vmvnq insns in mve.md are modified to use 'not' instead of unspec expression to support one_cmpl2. The one_cmpl2 expander is added to vec-common.md. 2020-12-11 Christophe Lyon gcc/ * config/arm/iterators.md (VDQNOTM2): New mode iterator. (supf): Remove VMVNQ_S and VMVNQ_U. (VMVNQ): Remove. * config/arm/mve.md (mve_vmvnq_u): New entry for vmvn instruction using expression not. (mve_vmvnq_s): New expander. * config/arm/neon.md (one_cmpl2): Renamed into one_cmpl2_neon. * config/arm/unspecs.md (VMVNQ_S, VMVNQ_U): Remove. * config/arm/vec-common.md (one_cmpl2): New expander. gcc/testsuite/ * gcc.target/arm/simd/mve-vmvn.c: Add tests for vmvn. --- gcc/config/arm/iterators.md | 3 +- gcc/config/arm/mve.md | 14 +++++--- gcc/config/arm/neon.md | 4 +-- gcc/config/arm/unspecs.md | 2 -- gcc/config/arm/vec-common.md | 6 ++++ gcc/testsuite/gcc.target/arm/simd/mve-vmvn.c | 35 ++++++++++++++++++++ 6 files changed, 54 insertions(+), 10 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arm/simd/mve-vmvn.c diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md index 26351e0ed8e..036a939e2ee 100644 --- a/gcc/config/arm/iterators.md +++ b/gcc/config/arm/iterators.md @@ -1216,7 +1216,7 @@ (define_int_attr supf [(VCVTQ_TO_F_S "s") (VCVTQ_TO_F_U "u") (VREV16Q_S "s") (VREV16Q_U "u") (VMVNQ_N_S "s") (VMVNQ_N_U "u") (VCVTAQ_U "u") (VCVTAQ_S "s") (VREV64Q_S "s") - (VREV64Q_U "u") (VMVNQ_S "s") (VMVNQ_U "u") + (VREV64Q_U "u") (VDUPQ_N_U "u") (VDUPQ_N_S"s") (VADDVQ_S "s") (VADDVQ_U "u") (VADDVQ_S "s") (VADDVQ_U "u") (VMOVLTQ_U "u") (VMOVLTQ_S "s") (VMOVLBQ_S "s") @@ -1476,7 +1476,6 @@ (define_int_iterator VCVTQ_FROM_F [VCVTQ_FROM_F_S VCVTQ_FROM_F_U]) (define_int_iterator VREV16Q [VREV16Q_U VREV16Q_S]) (define_int_iterator VCVTAQ [VCVTAQ_U VCVTAQ_S]) -(define_int_iterator VMVNQ [VMVNQ_U VMVNQ_S]) (define_int_iterator VDUPQ_N [VDUPQ_N_U VDUPQ_N_S]) (define_int_iterator VCLZQ [VCLZQ_U VCLZQ_S]) (define_int_iterator VADDVQ [VADDVQ_U VADDVQ_S]) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 0505537e206..86d7fc64763 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -433,16 +433,22 @@ ;; ;; [vmvnq_u, vmvnq_s]) ;; -(define_insn "mve_vmvnq_" +(define_insn "mve_vmvnq_u" [ (set (match_operand:MVE_2 0 "s_register_operand" "=w") - (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")] - VMVNQ)) + (not:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w"))) ] "TARGET_HAVE_MVE" - "vmvn %q0, %q1" + "vmvn\t%q0, %q1" [(set_attr "type" "mve_move") ]) +(define_expand "mve_vmvnq_s" + [ + (set (match_operand:MVE_2 0 "s_register_operand") + (not:MVE_2 (match_operand:MVE_2 1 "s_register_operand"))) + ] + "TARGET_HAVE_MVE" +) ;; ;; [vdupq_n_u, vdupq_n_s]) diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index e1263b00b39..f58d4f5479c 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -756,7 +756,7 @@ [(set_attr "type" "neon_logic")] ) -(define_insn "one_cmpl2" +(define_insn "one_cmpl2_neon" [(set (match_operand:VDQ 0 "s_register_operand" "=w") (not:VDQ (match_operand:VDQ 1 "s_register_operand" "w")))] "TARGET_NEON" @@ -3240,7 +3240,7 @@ (match_operand:VDQIW 1 "s_register_operand")] "TARGET_NEON" { - emit_insn (gen_one_cmpl2 (operands[0], operands[1])); + emit_insn (gen_one_cmpl2_neon (operands[0], operands[1])); DONE; }) diff --git a/gcc/config/arm/unspecs.md b/gcc/config/arm/unspecs.md index 8a4389a57c3..e5816459f12 100644 --- a/gcc/config/arm/unspecs.md +++ b/gcc/config/arm/unspecs.md @@ -550,8 +550,6 @@ VREV64Q_U VQABSQ_S VNEGQ_S - VMVNQ_S - VMVNQ_U VDUPQ_N_U VDUPQ_N_S VCLZQ_U diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-common.md index 030ed82ca7e..37ff518fc4e 100644 --- a/gcc/config/arm/vec-common.md +++ b/gcc/config/arm/vec-common.md @@ -193,3 +193,9 @@ (match_operand:VDQ 2 "s_register_operand" "")))] "ARM_HAVE__ARITH" ) + +(define_expand "one_cmpl2" + [(set (match_operand:VDQ 0 "s_register_operand") + (not:VDQ (match_operand:VDQ 1 "s_register_operand")))] + "ARM_HAVE__ARITH" +) diff --git a/gcc/testsuite/gcc.target/arm/simd/mve-vmvn.c b/gcc/testsuite/gcc.target/arm/simd/mve-vmvn.c new file mode 100644 index 00000000000..73e897a6245 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/mve-vmvn.c @@ -0,0 +1,35 @@ +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O3" } */ + +#include + +#define FUNC(SIGN, TYPE, BITS, NB, OP, NAME) \ + void test_ ## NAME ##_ ## SIGN ## BITS ## x ## NB (TYPE##BITS##_t * __restrict__ dest, TYPE##BITS##_t *a) { \ + int i; \ + for (i=0; i