From fd4512e9fa50ca14154ce6981c13a9c45556025d Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 8 Oct 2022 11:04:05 +0100
Subject: [PATCH] add XER bits to register enums

---
 src/openpower/decoder/power_enums.py | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py
index 081a703c..f3da7119 100644
--- a/src/openpower/decoder/power_enums.py
+++ b/src/openpower/decoder/power_enums.py
@@ -414,6 +414,13 @@ class RegType(Enum):
     BI = CR_BIT
     BT = CR_BIT
 
+    XER_BIT = 4   # XER bits, includes OV, OV32, SO, CA, CA32
+    OV = XER_BIT
+    OV32 = XER_BIT
+    CA = XER_BIT
+    CA32 = XER_BIT
+    SO = XER_BIT
+
     @classmethod
     def _missing_(cls, value):
         if isinstance(value, SVExtraReg):
-- 
2.30.2