From fd54fc85aa6ad6f6d904ee7d7cf9955257fa703f Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Fri, 23 Aug 2019 08:52:07 +0200 Subject: [PATCH] ac: add has_ls_vgpr_init_bug to ac_gpu_info MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen Reviewed-by: Marek Olšák --- src/amd/common/ac_gpu_info.c | 3 +++ src/amd/common/ac_gpu_info.h | 1 + src/gallium/drivers/radeonsi/si_pipe.c | 2 -- src/gallium/drivers/radeonsi/si_pipe.h | 1 - src/gallium/drivers/radeonsi/si_shader.c | 2 +- src/gallium/drivers/radeonsi/si_state_draw.c | 2 +- 6 files changed, 6 insertions(+), 5 deletions(-) diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c index b366dc6be19..5fb1e26376a 100644 --- a/src/amd/common/ac_gpu_info.c +++ b/src/amd/common/ac_gpu_info.c @@ -488,6 +488,9 @@ bool ac_query_gpu_info(int fd, void *dev_p, info->family == CHIP_VEGA10 || info->family == CHIP_RAVEN; + info->has_ls_vgpr_init_bug = info->family == CHIP_VEGA10 || + info->family == CHIP_RAVEN; + /* Get the number of good compute units. */ info->num_good_compute_units = 0; for (i = 0; i < info->max_se; i++) diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h index ba09f38edb8..c850da22d4e 100644 --- a/src/amd/common/ac_gpu_info.h +++ b/src/amd/common/ac_gpu_info.h @@ -162,6 +162,7 @@ struct radeon_info { bool has_gfx9_scissor_bug; bool has_tc_compat_zrange_bug; bool has_msaa_sample_loc_bug; + bool has_ls_vgpr_init_bug; }; bool ac_query_gpu_info(int fd, void *dev_p, diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c index d3dcab3ccce..fef44836ea2 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.c +++ b/src/gallium/drivers/radeonsi/si_pipe.c @@ -1135,8 +1135,6 @@ radeonsi_screen_create_impl(struct radeon_winsys *ws, #include "si_debug_options.h" } - sscreen->has_ls_vgpr_init_bug = sscreen->info.family == CHIP_VEGA10 || - sscreen->info.family == CHIP_RAVEN; sscreen->use_ngg = sscreen->info.chip_class >= GFX10; sscreen->use_ngg_streamout = sscreen->info.chip_class >= GFX10; diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h index 2d0b83fcf33..7acef0cfef4 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.h +++ b/src/gallium/drivers/radeonsi/si_pipe.h @@ -495,7 +495,6 @@ struct si_screen { bool has_out_of_order_rast; bool assume_no_z_fights; bool commutative_blend_add; - bool has_ls_vgpr_init_bug; bool dpbb_allowed; bool dfsm_allowed; bool llvm_has_working_vgpr_indexing; diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c index b8609e49fe1..28003d1bad2 100644 --- a/src/gallium/drivers/radeonsi/si_shader.c +++ b/src/gallium/drivers/radeonsi/si_shader.c @@ -7406,7 +7406,7 @@ static void si_build_vs_prolog_function(struct si_shader_context *ctx, si_init_exec_from_input(ctx, 3, 0); if (key->vs_prolog.as_ls && - ctx->screen->has_ls_vgpr_init_bug) { + ctx->screen->info.has_ls_vgpr_init_bug) { /* If there are no HS threads, SPI loads the LS VGPRs * starting at VGPR 0. Shift them back to where they * belong. diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c index 788697db02e..586925ef727 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.c +++ b/src/gallium/drivers/radeonsi/si_state_draw.c @@ -1833,7 +1833,7 @@ static void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *i } if (sctx->tes_shader.cso && - sctx->screen->has_ls_vgpr_init_bug) { + sctx->screen->info.has_ls_vgpr_init_bug) { /* Determine whether the LS VGPR fix should be applied. * * It is only required when num input CPs > num output CPs, -- 2.30.2